Angelo Jacobo
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3bafed0015
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add more comments
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2024-03-25 21:21:01 +08:00 |
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Angelo Jacobo
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4f73cf0a7a
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add more comments
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2024-03-24 15:05:14 +08:00 |
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Angelo Jacobo
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775a9ad1fe
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add more comments
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2024-03-24 13:39:29 +08:00 |
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Angelo Jacobo
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4e557d795b
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add more comments
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2024-03-23 11:48:01 +08:00 |
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Angelo Jacobo
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2c560b65ba
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add more comments
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2024-03-23 11:05:00 +08:00 |
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Angelo Jacobo
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910a4d00a3
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add more comments
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2024-03-23 08:42:22 +08:00 |
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Angelo Jacobo
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22bd2f1118
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add more comments
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2024-03-22 19:50:14 +08:00 |
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Angelo Jacobo
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cf3bc8c629
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added more comments
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2024-03-22 18:30:51 +08:00 |
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AngeloJacobo
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9a88f5540c
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fix displayed report
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2023-11-26 13:21:15 +08:00 |
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AngeloJacobo
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292f94c530
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make 2nd wishbone removable via cyc line
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2023-11-18 13:34:27 +08:00 |
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AngeloJacobo
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c514d492f1
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changed to picosecond-based instead of nanoseconds
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2023-11-14 14:11:40 +08:00 |
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AngeloJacobo
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33ec101b79
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resolve bug "Conflicting initialization values for \index"
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2023-11-11 10:18:15 +08:00 |
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AngeloJacobo
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20953ee65f
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fixed bug when ODELAY is not supported, clean file header and description
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2023-11-09 13:25:39 +08:00 |
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AngeloJacobo
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8c5c5e30cc
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now passes internal test calibration on klusterboard
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2023-09-15 19:58:12 +08:00 |
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AngeloJacobo
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20db6352e2
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added write read test after calibration
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2023-09-08 17:15:34 +08:00 |
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AngeloJacobo
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de4fb994b4
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add debug lines and update wb2 registers
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2023-09-05 20:17:10 +08:00 |
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AngeloJacobo
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03a1da2ce7
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add calibration when DQS toggles early than DQ
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2023-09-05 18:31:10 +08:00 |
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AngeloJacobo
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8f3d673e3d
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fixed bug when issue write calibration has to be repeated
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2023-08-22 16:40:44 +08:00 |
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AngeloJacobo
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9769a7cfaa
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pass formal for 8-lane config and pass verilator linting
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2023-08-20 11:07:22 +08:00 |
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AngeloJacobo
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36c93689e5
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redo read/write calibration if data read is wrong
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2023-08-17 11:27:23 +08:00 |
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AngeloJacobo
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b3ab21a6d5
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:12:49 +08:00 |
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AngeloJacobo
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e9f1ab4971
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modify debug port logic for wbscope
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2023-08-04 07:57:09 +08:00 |
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AngeloJacobo
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1bfd851a6e
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pass formal with LANES either 1,2,4,8
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2023-08-04 07:49:25 +08:00 |
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AngeloJacobo
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2c73f38f99
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added debug port and max function for int type
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2023-08-01 15:58:58 +08:00 |
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AngeloJacobo
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d5f1d600ea
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resolve verilator warnings and add option YOSYS for not using input real in functions
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2023-07-24 17:27:17 +08:00 |
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AngeloJacobo
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7142dd9cdb
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added more registers and formal assertions to wb2
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2023-07-19 18:46:36 +08:00 |
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AngeloJacobo
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97e740139f
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resolved vivado warnings
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2023-07-17 21:38:20 +08:00 |
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AngeloJacobo
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019722bc70
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resolve warnings and errors from verilator linting
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2023-07-16 08:17:55 +08:00 |
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AngeloJacobo
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47766cb8e8
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added wishbone 2 and formally verified it
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2023-07-13 18:41:25 +08:00 |
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AngeloJacobo
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5904a4910d
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shortened formal depth from 9 to 7
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2023-07-09 09:34:03 +08:00 |
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AngeloJacobo
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b03ca1864f
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shortened formal depth from 17 to 9
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2023-07-08 10:19:58 +08:00 |
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AngeloJacobo
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b3c9bdb650
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pass test for timing params with depth of 9
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2023-07-06 20:29:50 +08:00 |
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AngeloJacobo
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ce3ca7e158
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pre-refresh delay is now flexible and not fixed. Separated formal properties for testing time parameters
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2023-07-05 16:35:57 +08:00 |
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AngeloJacobo
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217770b977
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verified precharge and activate cmds, fixed bug in write_calib cmd
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2023-07-02 06:38:33 +08:00 |
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AngeloJacobo
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760c75d238
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passes optimized pipeline stall control and passed fwb_slave properties
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2023-06-29 12:56:24 +08:00 |
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AngeloJacobo
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2cfbba6d28
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change ff to unix
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2023-06-24 08:04:21 +08:00 |
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AngeloJacobo
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2221a739db
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add 2 clocks in prestall delay to pass tWR violation, add more asserts for fwb_slave
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2023-06-24 07:46:09 +08:00 |
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AngeloJacobo
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0ffdacf6e7
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add logic for write wb_ack, wb_sel, and aux
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2023-06-22 19:49:05 +08:00 |
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AngeloJacobo
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0923fdc0b6
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add formal assertions using fifo to prove every wb request has a corresponding read/write command output
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2023-06-15 17:43:15 +08:00 |
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AngeloJacobo
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053a511144
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set write-to-read delay for all banks for every write
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2023-06-10 08:19:16 +08:00 |
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AngeloJacobo
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c3707dab53
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made delay tap loadable and made delay more flexible to use all 32 taps for both dqs and dq
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2023-06-08 11:01:56 +08:00 |
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Angelo Jacobo
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6127bba77a
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fixed data alignment for write operation, fixed CL and CWL for 100MHz:400MHz clk
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2023-06-01 19:18:41 +08:00 |
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Angelo Jacobo
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9e529131c0
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fixed error "added_read_pipe has multiple drivers"
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2023-05-29 20:52:48 +08:00 |
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Angelo Jacobo
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a56e6a8a24
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changed write calibration pattern with high autocorrel stat
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2023-05-29 16:40:41 +08:00 |
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Angelo Jacobo
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ab26902f7a
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include only the controller (phy is now a separate module)
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2023-05-28 16:18:14 +08:00 |
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Angelo Jacobo
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1e89a236df
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fixed implementation errors in Vivado
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2023-05-25 19:13:30 +08:00 |
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Angelo Jacobo
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8e6c422689
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complete read and write calibration
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2023-05-18 10:45:26 +08:00 |
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Angelo Jacobo
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c33bc40bd3
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Update ddr3_controller.v
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2023-05-11 15:35:34 +08:00 |
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Angelo Jacobo
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9be5b5a616
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Update ddr3_controller.v
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2023-05-11 14:49:47 +08:00 |
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Angelo Jacobo
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f3c4b1b465
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Update ddr3_controller.v
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2023-05-10 15:23:48 +08:00 |