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UberDDR3
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zero all delays

This commit is contained in:
Angelo Jacobo 2024-04-28 16:21:07 +08:00
parent 926e167376
commit a14afa4c4b
1 changed files with 1 additions and 1 deletions
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testbench/ddr3.sv
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@ -138,7 +138,7 @@ module ddr3 (
parameter feature_truebl4 = 0; parameter feature_truebl4 = 0;
parameter feature_odt_hi = 0; parameter feature_odt_hi = 0;
parameter PERTCKAVG=TDLLK; parameter PERTCKAVG=TDLLK;
parameter FLY_BY_DELAY = 1600, DQ_DELAY = 0; parameter FLY_BY_DELAY = 0, DQ_DELAY = 0;
// text macros // text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS `define DQ_PER_DQS DQ_BITS/DQS_BITS