From a14afa4c4b3a3edcd2626081fdd7db0d49c1398e Mon Sep 17 00:00:00 2001
From: Angelo Jacobo <jacobo.angeloECE@gmail.com>
Date: Sun, 28 Apr 2024 16:21:07 +0800
Subject: [PATCH] zero all delays

---
 testbench/ddr3.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testbench/ddr3.sv b/testbench/ddr3.sv
index d5e3c16..c6f1fba 100644
--- a/testbench/ddr3.sv
+++ b/testbench/ddr3.sv
@@ -138,7 +138,7 @@ module ddr3 (
     parameter feature_truebl4 = 0;
     parameter feature_odt_hi = 0;
     parameter PERTCKAVG=TDLLK;
-    parameter FLY_BY_DELAY = 1600, DQ_DELAY = 0;
+    parameter FLY_BY_DELAY = 0, DQ_DELAY = 0;
     
     // text macros
     `define DQ_PER_DQS DQ_BITS/DQS_BITS