From 710d47701443367e819bc648d195b9bdea6efda7 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sat, 3 Jun 2023 14:31:29 +0800 Subject: [PATCH] added vivado gtkw for micron model simulation --- ddr3_dimm_micron_sim_behav.wcfg | 188 ++++++++++++++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 ddr3_dimm_micron_sim_behav.wcfg diff --git a/ddr3_dimm_micron_sim_behav.wcfg b/ddr3_dimm_micron_sim_behav.wcfg new file mode 100644 index 0000000..312a19f --- /dev/null +++ b/ddr3_dimm_micron_sim_behav.wcfg @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + + + + + Model File + label + + + i_controller_clk + i_controller_clk + + + i_ddr3_clk + i_ddr3_clk + + + i_ref_clk + i_ref_clk + + + i_rst_n + i_rst_n + + + i_wb_cyc + i_wb_cyc + + + i_wb_stb + i_wb_stb + + + i_wb_we + i_wb_we + + + i_wb_addr[23:0] + i_wb_addr[23:0] + + + i_wb_data[511:0] + i_wb_data[511:0] + + + o_wb_stall + o_wb_stall + + + o_wb_ack + o_wb_ack + + + o_wb_data[511:0] + o_wb_data[511:0] + HEXRADIX + + + ck_en + ck_en + + + cs_n + cs_n + + + odt + odt + + + ras_n + ras_n + + + cas_n + cas_n + + + we_n + we_n + + + reset_n + reset_n + + + addr[13:0] + addr[13:0] + + + ba_addr[2:0] + ba_addr[2:0] + + + dq[63:0] + dq[63:0] + + + i_controller_clk + i_controller_clk + + + i_ddr3_clk + i_ddr3_clk + + + dqs[7:0] + dqs[7:0] + + + + dqs_n[7:0] + dqs_n[7:0] + + + o_ddr3_clk_p + o_ddr3_clk_p + + + o_ddr3_clk_n + o_ddr3_clk_n + + + DDR3 Controller + label + + + state_calibrate[4:0] + state_calibrate[4:0] + + + lane[6:0] + lane[6:0] + + + instruction_address[4:0] + instruction_address[4:0] + + + dqs_store[39:0] + dqs_store[39:0] + BINARYRADIX + + + dqs_start_index[5:0] + dqs_start_index[5:0] + + + dqs_start_index_repeat[0:0] + dqs_start_index_repeat[0:0] + + + i_phy_iserdes_data[511:0] + i_phy_iserdes_data[511:0] + HEXRADIX + + + i_phy_iserdes_dqs[63:0] + i_phy_iserdes_dqs[63:0] + BINARYRADIX + + + i_phy_iserdes_bitslip_reference[63:0] + i_phy_iserdes_bitslip_reference[63:0] + + + i_phy_idelayctrl_rdy + i_phy_idelayctrl_rdy + +