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UberDDR3
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UberDDR3/testbench/xsim/vlog.prj

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vivado simulation files directory are now relative, can now run sim anywhere
2025-03-01 07:39:54 +01:00
verilog xil_defaultlib --include "../../testbench" \
modified vivado simulation files
2025-05-24 11:33:49 +02:00
"../../testbench/models/IDELAYCTRL_model.v" \
"../../testbench/models/IDELAYE2_model.v" \
use SIM_MODEL directive to use models during vivado simulation
2025-05-25 03:03:16 +02:00
"../../testbench/models/IOBUF_DCIEN_model.v" \
modified vivado simulation files
2025-05-24 11:33:49 +02:00
"../../testbench/models/IOBUF_model.v" \
"../../testbench/models/IOBUFDS_DCIEN_model.v" \
"../../testbench/models/IOBUFDS_model.v" \
"../../testbench/models/ISERDESE2_model.v" \
"../../testbench/models/OBUFDS_model.v" \
"../../testbench/models/ODELAYE2_model.v" \
"../../testbench/models/OSERDESE2_model.v" \
"../../testbench/models/OBUF_model.v" \
vivado simulation files directory are now relative, can now run sim anywhere
2025-03-01 07:39:54 +01:00
"../../rtl/ddr3_controller.v" \
"../../rtl/ddr3_phy.v" \
"../../rtl/ddr3_top.v" \
add vivado batch sim script (just run run_batch.sh)
2024-07-28 11:39:21 +02:00
vivado simulation files directory are now relative, can now run sim anywhere
2025-03-01 07:39:54 +01:00
sv xil_defaultlib --include "../../testbench" \
"../../testbench/ddr3.sv" \
"../../testbench/ddr3_module.sv" \
"../../testbench/ddr3_dimm_micron_sim.sv" \
add vivado batch sim script (just run run_batch.sh)
2024-07-28 11:39:21 +02:00
vivado simulation files directory are now relative, can now run sim anywhere
2025-03-01 07:39:54 +01:00
verilog xil_defaultlib "../../testbench/xsim/glbl.v"
add vivado batch sim script (just run run_batch.sh)
2024-07-28 11:39:21 +02:00
nosort