Cho Moon efb7aa1e8e mark black box cells as such ... Signed-off-by: Cho Moon <cmoon@precisioninno.com>		2025-01-11 01:11:28 +00:00
..
Verilog.i	verilog reader cleanups	2024-12-28 15:48:18 -08:00
Verilog.tcl	update copyright	2024-01-11 16:34:49 -08:00
VerilogLex.ll	Fixes constant integer verilog parsing	2024-10-08 20:40:07 +00:00
VerilogParse.yy	Fixes memory leak in verilog attribute code.	2024-04-22 21:54:12 +00:00
VerilogReader.cc	mark black box cells as such	2025-01-11 01:11:28 +00:00
VerilogReaderPvt.hh	Merge remote-tracking branch 'origin/master' into secure-sta-read-verilog-enh	2025-01-09 02:01:38 +00:00
VerilogWriter.cc	write_verilog unconnected wire dcls for non-top level modules	2024-10-21 11:33:11 -07:00