OpenSTA/verilog
Jaehyun Kim e5d8d8c970 test: Remove empty-body assertions and fix test issues from review feedback
Remove useless empty-body if-blocks that check file size/existence without
doing anything, replacing them with meaningful puts output where appropriate.
Split monolithic verilog test files into individual per-test files with
their own .ok golden files. Update .ok files to match actual output.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-22 18:52:36 +09:00
..
test test: Remove empty-body assertions and fix test issues from review feedback 2026-02-22 18:52:36 +09:00
Verilog.i rm write_verilog -sort 2025-12-12 09:40:45 -07:00
Verilog.tcl rm write_verilog -sort 2025-12-12 09:40:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogReader.cc Fix C++20 warning (#337) 2025-11-21 07:02:35 -08:00
VerilogReader.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rm write_verilog -sort 2025-12-12 09:40:45 -07:00