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OpenSTA/include/sta
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Deepashree Sengupta c887b2e4b3
Bias pin handling (#409) 
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 		2026-04-07 11:00:01 -07:00
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FilterObjects.hh get_* -filter allow true/false, '.' in glob pattern resolves #416 2026-04-04 16:19:41 -07:00
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PortDirection.hh Bias pin handling (#409) 2026-04-07 11:00:01 -07:00
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