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Deepashree Sengupta
c887b2e4b3
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog Signed-off-by: dsengupta0628 <[email protected]> * unnecessary space in orig verilog Signed-off-by: dsengupta0628 <[email protected]> * Update to use well supplies rather than bias pins Signed-off-by: dsengupta0628 <[email protected]> --------- Signed-off-by: dsengupta0628 <[email protected]>