57 lines
1.5 KiB
Tcl
57 lines
1.5 KiB
Tcl
# Test write verilog with multiple cell types (Nangate45)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_test1.v
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link_design verilog_test1
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# Add various cell types to exercise more writer paths
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set net_a [make_net wire_a]
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set net_b [make_net wire_b]
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set net_c [make_net wire_c]
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set net_d [make_net wire_d]
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set net_e [make_net wire_e]
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# NAND gate
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set inst_nand [make_instance nand1 NangateOpenCellLibrary/NAND2_X1]
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connect_pin wire_a nand1/A1
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connect_pin wire_b nand1/A2
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# NOR gate
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set inst_nor [make_instance nor1 NangateOpenCellLibrary/NOR2_X1]
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connect_pin wire_c nor1/A1
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connect_pin wire_d nor1/A2
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# Another buffer with different drive
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set inst_buf [make_instance buf_x4 NangateOpenCellLibrary/BUF_X4]
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connect_pin wire_e buf_x4/A
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puts "cells after additions: [llength [get_cells *]]"
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puts "nets after additions: [llength [get_nets *]]"
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# Write basic verilog
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set out1 [make_result_file verilog_write_nangate_out1.v]
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write_verilog $out1
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diff_files $out1 verilog_write_nangate_out1.vok
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# Write with pwr_gnd
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set out2 [make_result_file verilog_write_nangate_out2.v]
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write_verilog -include_pwr_gnd $out2
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diff_files $out2 verilog_write_nangate_out2.vok
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# Cleanup added instances/nets
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disconnect_pin wire_a nand1/A1
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disconnect_pin wire_b nand1/A2
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disconnect_pin wire_c nor1/A1
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disconnect_pin wire_d nor1/A2
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disconnect_pin wire_e buf_x4/A
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delete_instance nand1
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delete_instance nor1
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delete_instance buf_x4
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delete_net wire_a
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delete_net wire_b
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delete_net wire_c
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delete_net wire_d
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delete_net wire_e
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