69 lines
2.1 KiB
Tcl
69 lines
2.1 KiB
Tcl
# Test verilog reader with specify blocks, parameters, and defparams
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# Targets: VerilogReader.cc (parameter/specify/defparam paths)
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# VerilogLex.ll (lexer paths for specify, parameter, defparam keywords)
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# VerilogParse.yy (parser paths for specify blocks)
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source ../../test/helpers.tcl
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proc assert_file_nonempty {path} {
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if {![file exists $path] || [file size $path] <= 0} {
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error "expected non-empty file: $path"
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}
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}
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proc assert_file_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] < 0} {
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error "expected '$token' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test: Read verilog with specify blocks and parameters
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#---------------------------------------------------------------
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puts "--- read verilog with specify/parameter ---"
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog ../../test/verilog_specify.v
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link_design counter
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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if {[llength $cells] != 0} {
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error "unexpected cell count in specify test: [llength $cells]"
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}
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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if {[llength $nets] < 4} {
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error "unexpected net count in specify test: [llength $nets]"
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}
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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if {[llength $ports] != 4} {
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error "unexpected port count in specify test: [llength $ports]"
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}
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set src_in [open ../../test/verilog_specify.v r]
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set src_text [read $src_in]
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close $src_in
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foreach token {specify parameter defparam} {
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if {[string first $token $src_text] < 0} {
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error "missing expected token '$token' in source verilog_specify.v"
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}
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}
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#---------------------------------------------------------------
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# Write and verify
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#---------------------------------------------------------------
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puts "--- write_verilog ---"
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set outfile [make_result_file verilog_specify_out.v]
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write_verilog $outfile
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assert_file_nonempty $outfile
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assert_file_contains $outfile "module counter"
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assert_file_contains $outfile "input clk;"
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assert_file_contains $outfile "output out;"
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assert_file_contains $outfile "endmodule"
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