47 lines
587 B
Plaintext
47 lines
587 B
Plaintext
module network_hier_test (clk,
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in1,
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in2,
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in3,
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out1,
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out2);
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input clk;
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input in1;
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input in2;
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input in3;
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output out1;
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output out2;
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wire w1;
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wire w2;
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wire w3;
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wire w4;
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wire w5;
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BUF_X2 buf_out1 (.A(w5),
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.Z(out1));
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INV_X1 inv1 (.A(w3),
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.ZN(w4));
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DFF_X1 reg1 (.D(w4),
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.CK(clk),
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.Q(w5));
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sub_block sub1 (.A(w1),
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.B(in2),
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.Y(w2));
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sub_block sub2 (.A(w2),
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.B(in3),
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.Y(w3));
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endmodule
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module sub_block (A,
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B,
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Y);
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input A;
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input B;
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output Y;
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wire n1;
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AND2_X1 and_gate (.A1(A),
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.A2(B),
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.ZN(n1));
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endmodule
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