85 lines
2.8 KiB
Tcl
85 lines
2.8 KiB
Tcl
# Test 2: Write with remove_cells for multi-gate design
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source ../../test/helpers.tcl
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suppress_msg 1140
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proc assert_file_nonempty {path} {
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if {![file exists $path]} {
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error "expected non-empty file: $path"
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}
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string length $text] <= 0} {
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error "expected non-empty file: $path"
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}
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}
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proc assert_file_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] < 0} {
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error "expected '$token' in $path"
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}
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}
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proc assert_file_not_has_cell {path cell_name} {
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set in [open $path r]
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set text [read $in]
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close $in
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set cell_pat [format {(^|[^A-Za-z0-9_])%s([^A-Za-z0-9_]|$)} $cell_name]
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if {[regexp -- $cell_pat $text]} {
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error "did not expect cell '$cell_name' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test 2: Write with remove_cells for multi-gate design
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#---------------------------------------------------------------
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puts "--- Test 2: remove_cells on multi-gate design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../dcalc/test/dcalc_multidriver_test.v
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link_design dcalc_multidriver_test
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set out_md_basic [make_result_file verilog_remove_md_basic.v]
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write_verilog $out_md_basic
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# Remove INV_X1
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set out_md_inv [make_result_file verilog_remove_md_inv.v]
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write_verilog -remove_cells {INV_X1} $out_md_inv
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assert_file_nonempty $out_md_inv
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assert_file_not_has_cell $out_md_inv INV_X1
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assert_file_contains $out_md_inv "module dcalc_multidriver_test"
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# Remove AND2_X1
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set out_md_and [make_result_file verilog_remove_md_and.v]
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write_verilog -remove_cells {AND2_X1} $out_md_and
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assert_file_nonempty $out_md_and
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assert_file_not_has_cell $out_md_and AND2_X1
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assert_file_contains $out_md_and "module dcalc_multidriver_test"
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# Remove NAND2_X1 and NOR2_X1
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set out_md_gates [make_result_file verilog_remove_md_gates.v]
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write_verilog -remove_cells {NAND2_X1 NOR2_X1} $out_md_gates
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assert_file_nonempty $out_md_gates
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assert_file_not_has_cell $out_md_gates NAND2_X1
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assert_file_not_has_cell $out_md_gates NOR2_X1
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assert_file_contains $out_md_gates "module dcalc_multidriver_test"
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diff_files verilog_remove_md_basic.vok $out_md_basic
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diff_files verilog_remove_md_inv.vok $out_md_inv
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diff_files verilog_remove_md_and.vok $out_md_and
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diff_files verilog_remove_md_gates.vok $out_md_gates
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_md_inv
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link_design dcalc_multidriver_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
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set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
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set_input_transition 0.1 [all_inputs]
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with_output_to_variable md_rep { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $md_rep]} {
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error "remove_cells multigate roundtrip timing report missing max path"
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}
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