104 lines
3.4 KiB
Tcl
104 lines
3.4 KiB
Tcl
# Test VerilogReader and VerilogWriter with isolated roundtrip scenarios.
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# Each scenario starts from a clean STA state to keep output stable.
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source ../../test/helpers.tcl
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proc load_nangate_design {verilog_file top_name} {
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global nangate_lib_loaded
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sta::clear_sta
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if { !$nangate_lib_loaded } {
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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set nangate_lib_loaded 1
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}
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read_verilog $verilog_file
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link_design $top_name
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}
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proc load_asap7_design {verilog_file top_name} {
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sta::clear_sta
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
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read_verilog $verilog_file
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link_design $top_name
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}
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############################################################
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# Scenario 1: Nangate write options
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############################################################
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puts "--- Nangate write options ---"
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set nangate_lib_loaded 0
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load_nangate_design ../../examples/example1.v top
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puts "cells: [llength [get_cells *]]"
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set out1 [make_result_file verilog_mm_default.v]
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write_verilog $out1
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set out2 [make_result_file verilog_mm_pwr.v]
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write_verilog -include_pwr_gnd $out2
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set out3 [make_result_file verilog_mm_sort.v]
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write_verilog -sort $out3
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set out4 [make_result_file verilog_mm_pwr_sort.v]
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write_verilog -include_pwr_gnd -sort $out4
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############################################################
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# Scenario 2: Nangate default roundtrip + timing/queries
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############################################################
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puts "--- Nangate default roundtrip ---"
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load_nangate_design $out1 top
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puts "re-read default cells: [llength [get_cells *]]"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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set_output_delay -clock clk 0 [get_ports out]
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set_input_transition 0.1 [all_inputs]
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report_checks
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report_checks -path_delay min
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report_checks -fields {slew cap input_pins fanout}
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foreach inst_name {r1 r2 r3 u1 u2} {
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set inst [get_cells $inst_name]
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puts "$inst_name ref=[get_property $inst ref_name]"
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}
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foreach net_name {r1q r2q u1z u2z} {
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report_net $net_name
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}
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############################################################
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# Scenario 3: Nangate alternative roundtrip inputs
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############################################################
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puts "--- Nangate pwr roundtrip ---"
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load_nangate_design $out2 top
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puts "re-read pwr cells: [llength [get_cells *]]"
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puts "--- Nangate sorted roundtrip ---"
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load_nangate_design $out3 top
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puts "re-read sorted cells: [llength [get_cells *]]"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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report_checks
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############################################################
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# Scenario 4: ASAP7 write options
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############################################################
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puts "--- ASAP7 write options ---"
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load_asap7_design ../../test/reg1_asap7.v top
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puts "asap7 cells: [llength [get_cells *]]"
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set out5 [make_result_file verilog_mm_asap7.v]
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write_verilog $out5
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set out6 [make_result_file verilog_mm_asap7_pwr.v]
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write_verilog -include_pwr_gnd $out6
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create_clock -name clk -period 500 {clk1 clk2 clk3}
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set_input_delay -clock clk 1 {in1 in2}
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set_output_delay -clock clk 1 [get_ports out]
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report_checks
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