109 lines
3.8 KiB
Tcl
109 lines
3.8 KiB
Tcl
# Test verilog writer with larger GCD design (sky130hd)
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# Targets: VerilogWriter.cc (writeModules, findHierChildren, writeChildren,
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# writeChild, writeInstPin, writeWireDcls, writePorts, writePortDcls,
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# verilogPortDir for various directions, findUnconnectedNetCount)
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# Also targets: VerilogReader.cc (bus port reading, large netlist parsing,
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# makeModuleInst, linkNetwork, various cell types, declaration handling)
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 1: Read and write GCD sky130hd design (large design)
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#---------------------------------------------------------------
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puts "--- Test 1: read GCD sky130hd ---"
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog ../../examples/gcd_sky130hd.v
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link_design gcd
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Check bus ports exist
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set req_msg_ports [get_ports req_msg*]
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puts "req_msg* ports: [llength $req_msg_ports]"
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set resp_msg_ports [get_ports resp_msg*]
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puts "resp_msg* ports: [llength $resp_msg_ports]"
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# Query specific ports
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foreach pname {clk reset req_val req_rdy resp_val resp_rdy} {
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set p [get_ports $pname]
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puts "$pname dir=[get_property $p direction]"
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}
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#---------------------------------------------------------------
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# Test 2: Write verilog - basic
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#---------------------------------------------------------------
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puts "--- Test 2: write_verilog basic ---"
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set out1 [make_result_file verilog_hier_basic.v]
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write_verilog $out1
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#---------------------------------------------------------------
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# Test 3: Write verilog with -include_pwr_gnd
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#---------------------------------------------------------------
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puts "--- Test 3: write_verilog -include_pwr_gnd ---"
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set out2 [make_result_file verilog_hier_pwr.v]
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write_verilog -include_pwr_gnd $out2
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diff_files verilog_hier_basic.vok $out1
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diff_files verilog_hier_pwr.vok $out2
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#---------------------------------------------------------------
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# Test 4: Write verilog with -remove_cells
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#---------------------------------------------------------------
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puts "--- Test 4: write_verilog -remove_cells ---"
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set out3 [make_result_file verilog_hier_remove.v]
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write_verilog -remove_cells {} $out3
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#---------------------------------------------------------------
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# Test 5: Read back the written verilog (roundtrip)
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#---------------------------------------------------------------
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puts "--- Test 5: read back written verilog ---"
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog $out1
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link_design gcd
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set cells2 [get_cells *]
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puts "roundtrip cells: [llength $cells2]"
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set nets2 [get_nets *]
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puts "roundtrip nets: [llength $nets2]"
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set ports2 [get_ports *]
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puts "roundtrip ports: [llength $ports2]"
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# Write again after roundtrip
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set out4 [make_result_file verilog_hier_roundtrip.v]
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write_verilog $out4
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#---------------------------------------------------------------
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# Test 6: Set up timing and report with bus ports
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#---------------------------------------------------------------
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puts "--- Test 6: timing with bus ports ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {reset req_val req_msg* resp_rdy}]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks
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report_checks -path_delay min
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report_checks -fields {slew cap input_pins fanout}
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#---------------------------------------------------------------
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# Test 7: Write verilog after timing setup (tests more writer paths)
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#---------------------------------------------------------------
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puts "--- Test 7: write after timing setup ---"
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set out5 [make_result_file verilog_hier_post_timing.v]
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write_verilog $out5
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set out6 [make_result_file verilog_hier_post_timing_pwr.v]
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write_verilog -include_pwr_gnd $out6
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