52 lines
1.7 KiB
Tcl
52 lines
1.7 KiB
Tcl
# Test 3: Write complex bus design
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# Exercises: writeWireDcls with bus nets (isBusName, parseBusName)
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 3: Write complex bus design
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# Exercises: writeWireDcls with bus nets (isBusName, parseBusName)
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#---------------------------------------------------------------
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puts "--- Test 3: write complex bus design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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set out3 [make_result_file verilog_escaped_complex.v]
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write_verilog $out3
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set out4 [make_result_file verilog_escaped_complex_pwr.v]
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write_verilog -include_pwr_gnd $out4
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# Read back complex bus design
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puts "--- roundtrip complex bus ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out3
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link_design verilog_complex_bus_test
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set rt2_cells [get_cells *]
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puts "complex roundtrip cells: [llength $rt2_cells]"
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set rt2_ports [get_ports *]
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puts "complex roundtrip ports: [llength $rt2_ports]"
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# Bus port queries after roundtrip
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set rt2_da [get_ports {data_a[*]}]
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puts "roundtrip data_a[*]: [llength $rt2_da]"
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set rt2_db [get_ports {data_b[*]}]
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puts "roundtrip data_b[*]: [llength $rt2_db]"
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set rt2_res [get_ports {result[*]}]
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puts "roundtrip result[*]: [llength $rt2_res]"
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# Timing after complex roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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set_input_transition 0.1 [all_inputs]
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report_checks
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