42 lines
1.2 KiB
Plaintext
42 lines
1.2 KiB
Plaintext
--- Test 1: write bus design ---
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cells: 12
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nets: 19
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ports: 11
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No differences found.
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No differences found.
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--- Test 2: roundtrip bus design ---
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roundtrip cells: 12
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roundtrip nets: 19
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roundtrip ports: 11
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roundtrip data_in[*]: 4
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roundtrip data_out[*]: 4
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Startpoint: data_in[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_in[0] (in)
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0.06 0.06 v buf0/Z (BUF_X1)
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0.03 0.08 v and0/ZN (AND2_X1)
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0.00 0.08 v reg0/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg0/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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