98 lines
3.3 KiB
Tcl
98 lines
3.3 KiB
Tcl
# Test verilog with net constants (1'b0, 1'b1), concatenation and part selects.
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 1: Read verilog with constants
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#---------------------------------------------------------------
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puts "--- Test 1: read verilog with constants ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_const_concat.v
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link_design verilog_const_concat
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Verify cells
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foreach cell_name {and_const or_const buf1 inv1 reg1 reg2 reg3 reg4} {
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set inst [get_cells $cell_name]
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set ref [get_property $inst ref_name]
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puts "$cell_name: ref=$ref"
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}
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#---------------------------------------------------------------
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# Test 2: Timing with constant nets
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#---------------------------------------------------------------
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puts "--- Test 2: timing with constants ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2 out3 out4}]
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set_input_transition 10 {in1 in2 in3 clk}
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report_checks
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report_checks -path_delay min
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out2]
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report_checks -fields {slew cap input_pins nets fanout}
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#---------------------------------------------------------------
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# Test 3: Write verilog
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#---------------------------------------------------------------
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puts "--- Test 3: write_verilog ---"
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set out1 [make_result_file verilog_const_concat_out.v]
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write_verilog $out1
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set out2 [make_result_file verilog_const_concat_pwr.v]
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write_verilog -include_pwr_gnd $out2
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#---------------------------------------------------------------
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# Test 4: report_net for constant-related nets
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#---------------------------------------------------------------
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puts "--- Test 4: net reports ---"
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foreach net_name {n1 n2 n3 n4} {
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report_net $net_name
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puts "report_net $net_name: done"
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}
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#---------------------------------------------------------------
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# Test 5: Report instances
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#---------------------------------------------------------------
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puts "--- Test 5: instance reports ---"
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foreach inst_name {and_const or_const buf1 inv1 reg1 reg2 reg3 reg4} {
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report_instance $inst_name
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}
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#---------------------------------------------------------------
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# Test 6: Re-read same file (exercises module re-definition path)
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#---------------------------------------------------------------
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puts "--- Test 6: re-read same verilog ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_const_concat.v
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read_verilog verilog_const_concat.v
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link_design verilog_const_concat
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puts "re-read cells: [llength [get_cells *]]"
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puts "re-read nets: [llength [get_nets *]]"
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#---------------------------------------------------------------
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# Test 7: Read back written verilog (roundtrip)
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#---------------------------------------------------------------
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puts "--- Test 7: roundtrip ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out1
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link_design verilog_const_concat
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puts "roundtrip cells: [llength [get_cells *]]"
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puts "roundtrip nets: [llength [get_nets *]]"
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