188 lines
5.7 KiB
Tcl
188 lines
5.7 KiB
Tcl
# Test verilog with complex bus/range constructs
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read complex bus verilog
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#---------------------------------------------------------------
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puts "--- Test 1: read complex bus verilog ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_complex_bus_test.v
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link_design verilog_complex_bus_test
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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#---------------------------------------------------------------
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# Test 2: Query 8-bit bus ports
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#---------------------------------------------------------------
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puts "--- Test 2: bus port queries ---"
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# Query bus ports
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set data_a_ports [get_ports data_a*]
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puts "data_a* ports: [llength $data_a_ports]"
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set data_b_ports [get_ports data_b*]
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puts "data_b* ports: [llength $data_b_ports]"
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set result_ports [get_ports result*]
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puts "result* ports: [llength $result_ports]"
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# Query individual bits
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foreach i {0 1 2 3 4 5 6 7} {
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set p [get_ports "data_a\[$i\]"]
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puts "data_a\[$i\]: [get_property $p direction]"
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}
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foreach i {0 1 2 3 4 5 6 7} {
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set p [get_ports "result\[$i\]"]
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puts "result\[$i\]: [get_property $p direction]"
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}
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# Scalar ports
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set carry_port [get_ports carry]
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puts "carry direction: [get_property $carry_port direction]"
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set overflow_port [get_ports overflow]
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puts "overflow direction: [get_property $overflow_port direction]"
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#---------------------------------------------------------------
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# Test 3: Query bus wires and nets
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#---------------------------------------------------------------
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puts "--- Test 3: bus wire queries ---"
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set stage1_nets [get_nets stage1*]
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puts "stage1* nets: [llength $stage1_nets]"
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set stage2_nets [get_nets stage2*]
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puts "stage2* nets: [llength $stage2_nets]"
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# Query individual wire bits
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foreach i {0 1 7} {
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set n [get_nets "stage1\[$i\]"]
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puts "stage1\[$i\]: [get_full_name $n]"
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set n [get_nets "stage2\[$i\]"]
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puts "stage2\[$i\]: [get_full_name $n]"
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}
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# Wildcard bus queries
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set wild_stage1 [get_nets {stage1[*]}]
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puts "stage1\[*\] nets: [llength $wild_stage1]"
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set wild_stage2 [get_nets {stage2[*]}]
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puts "stage2\[*\] nets: [llength $wild_stage2]"
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#---------------------------------------------------------------
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# Test 4: Query pins on cells connected to buses
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#---------------------------------------------------------------
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puts "--- Test 4: bus pin queries ---"
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# Pins on buffer cells
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set buf_a0_pins [get_pins buf_a0/*]
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puts "buf_a0 pins: [llength $buf_a0_pins]"
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foreach p $buf_a0_pins {
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puts " [get_full_name $p] dir=[get_property $p direction]"
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}
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# Pins on AND cells
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set and0_pins [get_pins and0/*]
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puts "and0 pins: [llength $and0_pins]"
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foreach p $and0_pins {
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puts " [get_full_name $p] dir=[get_property $p direction]"
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}
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# Pins on register cells
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set reg0_pins [get_pins reg0/*]
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puts "reg0 pins: [llength $reg0_pins]"
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foreach p $reg0_pins {
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puts " [get_full_name $p] dir=[get_property $p direction]"
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}
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# Wildcard pin queries
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set all_A_pins [get_pins */A]
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puts "*/A pins: [llength $all_A_pins]"
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set all_Z_pins [get_pins */Z]
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puts "*/Z pins: [llength $all_Z_pins]"
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set all_ZN_pins [get_pins */ZN]
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puts "*/ZN pins: [llength $all_ZN_pins]"
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set all_D_pins [get_pins */D]
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puts "*/D pins: [llength $all_D_pins]"
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set all_Q_pins [get_pins */Q]
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puts "*/Q pins: [llength $all_Q_pins]"
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set all_CK_pins [get_pins */CK]
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puts "*/CK pins: [llength $all_CK_pins]"
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#---------------------------------------------------------------
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# Test 5: Write verilog with bus ports
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# Exercises writeInstBusPin, writeInstBusPinBit paths
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#---------------------------------------------------------------
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puts "--- Test 5: write verilog with buses ---"
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set outfile [make_result_file verilog_complex_bus_out.v]
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write_verilog $outfile
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diff_files verilog_complex_bus_out.vok $outfile
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set outfile2 [make_result_file verilog_complex_bus_pwr.v]
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write_verilog -include_pwr_gnd $outfile2
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#---------------------------------------------------------------
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# Test 6: Timing analysis on bus design
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#---------------------------------------------------------------
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puts "--- Test 6: timing analysis ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {data_a[*]}]
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set_input_delay -clock clk 0 [get_ports {data_b[*]}]
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set_output_delay -clock clk 0 [get_ports {result[*]}]
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set_output_delay -clock clk 0 [get_ports carry]
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set_output_delay -clock clk 0 [get_ports overflow]
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set_input_transition 10 [all_inputs]
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report_checks
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report_checks -path_delay min
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# Specific paths through bus
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report_checks -from [get_ports {data_a[0]}] -to [get_ports {result[0]}]
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report_checks -from [get_ports {data_a[7]}] -to [get_ports {result[7]}]
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report_checks -to [get_ports carry]
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report_checks -to [get_ports overflow]
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report_checks -fields {slew cap input_pins fanout}
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#---------------------------------------------------------------
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# Test 7: Report nets on bus nets
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#---------------------------------------------------------------
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puts "--- Test 7: report_net on bus ---"
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foreach net {stage1[0] stage1[7] stage2[0] stage2[7] internal_carry internal_overflow} {
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report_net $net
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puts "report_net $net: done"
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}
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#---------------------------------------------------------------
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# Test 8: Fanin/fanout through bus
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#---------------------------------------------------------------
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puts "--- Test 8: fanin/fanout ---"
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set fi [get_fanin -to [get_ports {result[0]}] -flat]
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puts "fanin to result[0]: [llength $fi]"
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set fo [get_fanout -from [get_ports {data_a[0]}] -flat]
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puts "fanout from data_a[0]: [llength $fo]"
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set fi_cells [get_fanin -to [get_ports carry] -only_cells]
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puts "fanin cells to carry: [llength $fi_cells]"
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