55 lines
1.6 KiB
Tcl
55 lines
1.6 KiB
Tcl
# Test verilog reader with attributes and complex constructs.
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# Targets VerilogReader/VerilogLex/VerilogParse attribute parsing paths.
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 1: Read verilog with Yosys-style attributes
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#---------------------------------------------------------------
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puts "--- Test 1: Yosys attributes ---"
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog ../../test/verilog_attribute.v
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link_design counter
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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set pins [get_pins */*]
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puts "pins: [llength $pins]"
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# Check that cell attributes were stored
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foreach cell_name {_1415_} {
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set inst [get_cells $cell_name]
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set ref [get_property $inst ref_name]
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puts "$cell_name ref: $ref"
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}
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# Report timing to exercise attribute-bearing instances
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in]
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set_input_delay -clock clk 0 [get_ports reset]
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set_output_delay -clock clk 0 [get_ports out]
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report_checks
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report_checks -path_delay min
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report_checks -fields {slew cap input_pins}
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#---------------------------------------------------------------
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# Write verilog and read back
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#---------------------------------------------------------------
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puts "--- write_verilog and read back ---"
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set outfile [make_result_file verilog_attr_out.v]
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write_verilog $outfile
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# Write with include_pwr_gnd
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set outfile2 [make_result_file verilog_attr_pwr.v]
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write_verilog -include_pwr_gnd $outfile2
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