OpenSTA/verilog/test/verilog_advanced_out5.vok

module counter (clk,
    reset,
    in,
    out);
 input clk;
 input reset;
 input in;
 output out;

 wire mid;

 sky130_fd_sc_hd__dfrtp_1 _1415_ (.CLK(clk),
    .D(in),
    .Q(mid),
    .RESET_B(reset));
 sky130_fd_sc_hd__dfrtp_1 \_1416_[0]  (.CLK(clk),
    .D(mid),
    .Q(out),
    .RESET_B(reset));
endmodule