OpenSTA/network
Jaehyun Kim b6d598a119 test: strengthen assertions, add sorted SDC diff, and clean up tests
- Add diff_files_sorted to test/helpers.tcl for hash-order-independent
  SDC comparison (fixes non-deterministic write_sdc output ordering)
- Use diff_files_sorted in sdc_derate_disable_deep and
  sdc_port_delay_advanced tests
- Remove stale coverage percentages from test comments (Comment 1)
- Remove unnecessary catch blocks in search property tests (Comment 3)
- Strengthen load-only tests with actual data verification (Comment 8)
- Remove orphan .ok files for deleted monolithic tests (Comment 9)
- Add golden .sdcok/.libok/.vok/.sdfok files for SDC/liberty/verilog
  write-and-diff tests
- Add -B (clean rebuild) option to make_coverage_report.sh
- Replace (void) casts and EXPECT_TRUE(true) with real assertions in
  TestSdc.cc and TestVerilog.cc

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 11:50:23 +09:00
..
test test: strengthen assertions, add sorted SDC diff, and clean up tests 2026-02-23 11:50:23 +09:00
ConcreteLibrary.cc liberty bundle ports apply func's to members resolves #256 2025-06-16 16:45:21 +02:00
ConcreteNetwork.cc replace_cell w/spef memory issue 2025-12-02 14:29:55 -08:00
HpinDrvrLoad.cc update copyright 2025-01-21 18:54:33 -07:00
Link.tcl update copyright 2025-01-21 18:54:33 -07:00
Network.cc set_min/max_delay -from reg/D startpoint warning resolves #265 2025-07-03 17:08:44 -07:00
Network.i Verilog make pins for liberty pg_pins resolves #326 2025-11-07 11:55:43 -07:00
Network.tcl liberty bundle ports apply func's to members resolves #256 2025-06-16 16:45:21 +02:00
NetworkCmp.cc update copyright 2025-01-21 18:54:33 -07:00
NetworkEdit.i update copyright 2025-01-21 18:54:33 -07:00
NetworkEdit.tcl update copyright 2025-01-21 18:54:33 -07:00
ParseBus.cc update copyright 2025-01-21 18:54:33 -07:00
PortDirection.cc update copyright 2025-01-21 18:54:33 -07:00
SdcNetwork.cc spef support net missing divider escape resolves #311 2025-10-14 15:58:48 -07:00
VerilogNamespace.cc remove using std from headers 2025-04-11 16:59:48 -07:00