OpenSTA/verilog
Jaehyun Kim e57c8043cd test: Apply review feedback - part3
Remove unnecessary catch blocks from Tcl test files across all modules,
add report_checks after each set_wire_load_model in liberty_wireload,
rewrite liberty_sky130_corners for actual multi-corner timing analysis
with define_corners, and expand C++ tests (TestSearchIncremental 8→36,
TestPower 71→96, TestSpice 98→126 tests).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-20 13:05:07 +09:00
..
test test: Apply review feedback - part3 2026-02-20 13:05:07 +09:00
Verilog.i rm write_verilog -sort 2025-12-12 09:40:45 -07:00
Verilog.tcl rm write_verilog -sort 2025-12-12 09:40:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogReader.cc Fix C++20 warning (#337) 2025-11-21 07:02:35 -08:00
VerilogReader.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rm write_verilog -sort 2025-12-12 09:40:45 -07:00