OpenSTA/verilog
Jaehyun Kim 7173c10cc1 test: strengthen assertions, add sorted SDC diff, and clean up tests
- Split oversized test files to stay under 5,000 lines per file:
  TestSdc.cc → TestSdcClasses.cc, TestSdcStaInit.cc, TestSdcStaDesign.cc
  TestSearchStaDesign.cc → TestSearchStaDesign.cc, TestSearchStaDesignB.cc
  TestLibertyStaBasics.cc → TestLibertyStaBasics.cc, TestLibertyStaBasicsB.cc
  TestNetwork.cc → TestNetwork.cc, TestNetworkB.cc
- Replace ~200+ (void) casts with proper EXPECT_* assertions across all
  C++ test files (dcalc, liberty, network, sdc, search, power, spice, util)
- Remove ~55 SUCCEED() and EXPECT_TRUE(true) no-op assertions
- Fix 6 load-only Tcl tests by adding diff_files verification with
  22 new .sdcok golden reference files
- Delete 7 orphan .ok files with no matching .tcl tests
- Add how_to_write_good_tests.md and TODO6.md documenting test quality rules

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 17:36:45 +09:00
..
test test: strengthen assertions, add sorted SDC diff, and clean up tests 2026-02-23 17:36:45 +09:00
Verilog.i rm write_verilog -sort 2025-12-12 09:40:45 -07:00
Verilog.tcl rm write_verilog -sort 2025-12-12 09:40:45 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogReader.cc Fix C++20 warning (#337) 2025-11-21 07:02:35 -08:00
VerilogReader.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc rm write_verilog -sort 2025-12-12 09:40:45 -07:00