luke
/
OpenSTA
mirror of https://github.com/The-OpenROAD-Project/OpenSTA.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
OpenSTA/verilog
History
James Cherry 46a835a581 write_verilog assigns for nets with multiple output ports 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 		2021-10-08 10:51:05 -07:00
..
Verilog.i read_verilog/link_design support redirection 2021-07-09 11:25:05 -07:00
Verilog.tcl read_verilog/link_design support redirection 2021-07-09 11:25:05 -07:00
VerilogLex.ll update copyright 2021-06-25 10:25:49 -07:00
VerilogParse.yy update copyright 2021-06-25 10:25:49 -07:00
VerilogReader.cc verilog black box ports unknown/loads 2021-09-17 08:35:45 -07:00
VerilogReaderPvt.hh update copyright 2021-06-25 10:25:49 -07:00
VerilogWriter.cc write_verilog assigns for nets with multiple output ports 2021-10-08 10:51:05 -07:00