James Cherry
|
cc1bd6b5ab
|
TransRiseFall -> RiseFall
|
2019-11-11 15:30:19 -07:00 |
|
James Cherry
|
e05e7185ba
|
report_checks transition_time field -> slew
|
2019-06-24 08:35:04 -07:00 |
|
James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
|
2019-06-18 15:52:12 -07:00 |
|
James Cherry
|
d8146af755
|
remove autotools/configure support
|
2019-02-16 12:07:59 -08:00 |
|
James Cherry
|
316742202f
|
sync
|
2019-01-16 15:37:31 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
e1059eac12
|
find_timing_paths
|
2018-12-20 22:41:54 -08:00 |
|
James Cherry
|
f49dc75d32
|
sync
|
2018-12-05 14:18:41 -08:00 |
|
James Cherry
|
ddf897d4e6
|
report_power, pocv support
|
2018-11-26 09:15:52 -08:00 |
|
James Cherry
|
e9bde796ec
|
2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *)
|
2018-11-09 10:04:16 -08:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |