Commit Graph

18 Commits

Author SHA1 Message Date
James Cherry cc1bd6b5ab TransRiseFall -> RiseFall 2019-11-11 15:30:19 -07:00
James Cherry 6ac93c8c7d vertex_pin -> leaf_pin 2019-10-25 08:51:59 -07:00
James Cherry 73fb94a2dd set_units 2019-07-13 16:56:46 -07:00
James Cherry fa849908d7 set_cmd_units 2019-07-08 11:50:41 -07:00
James Cherry db6b650a52 splash include git sha1 2019-07-07 09:58:47 -07:00
James Cherry eb9fdd1be0 write verilog match liberty bus bit order 2019-07-02 07:07:34 -07:00
James Cherry 93f5f9d664 no need for virtuals in Concrete network objects 2019-06-28 13:38:56 -07:00
James Cherry 389b9b8276 set_data_check no -setup|-hold 2019-06-26 15:58:23 -07:00
James Cherry 15e759a992 get_lib_cells allow wildcard lib name 2019-06-23 21:38:01 -07:00
James Cherry 12494398e9 set_clock_sense -> set_sense, LibertyPort::driveResistance 2019-06-23 19:52:29 -07:00
James Cherry 5f3b10bdf2 mv GraphDelayCalc1::isDriver to Vertex 2019-06-12 21:41:33 -07:00
James Cherry 12ca613886 2.0.14 2019-04-18 18:01:10 -07:00
James Cherry d8146af755 remove autotools/configure support 2019-02-16 12:07:59 -08:00
James Cherry 316742202f sync 2019-01-16 15:37:31 -08:00
James Cherry b075ccc783 update copyright 2019-01-01 12:26:11 -08:00
James Cherry ddf897d4e6 report_power, pocv support 2018-11-26 09:15:52 -08:00
James Cherry e9bde796ec 2018/11/08 corners > 2 causes internal error, 2018/11/09 Verilog ignore attributes (* blah *) 2018-11-09 10:04:16 -08:00
James Cherry 1154fb89fd and then there was light... 2018-09-28 08:54:21 -07:00