James Cherry
|
3076b8d2ff
|
VertexIndex -> VertexId
|
2019-11-11 09:38:25 -07:00 |
|
James Cherry
|
184d044b02
|
replace Pool with ObjectTable
|
2019-11-11 08:28:42 -07:00 |
|
James Cherry
|
7af69066df
|
VerilogWriter use liberty bus port order
|
2019-07-02 16:33:31 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
88331ab9b1
|
Network bus brkts use library values
|
2019-06-28 11:51:43 -07:00 |
|
James Cherry
|
61333cd980
|
Network:bus_brkts_left/right
|
2019-06-26 17:14:31 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
|
2019-06-26 16:01:58 -07:00 |
|
James Cherry
|
e05e7185ba
|
report_checks transition_time field -> slew
|
2019-06-24 08:35:04 -07:00 |
|
James Cherry
|
dd8153c7f9
|
Network::isLeaf
|
2019-06-14 21:03:11 -07:00 |
|
James Cherry
|
9659c43590
|
network/sta replaceCell Cell support
|
2019-06-14 12:05:34 -07:00 |
|
James Cherry
|
a988588dac
|
sync
|
2019-05-19 17:06:06 -06:00 |
|
James Cherry
|
895c4c97c1
|
Sta::insert_buffer
|
2019-05-03 08:07:00 -07:00 |
|
James Cherry
|
2d519b4740
|
ucsd 20190410 seg fault accessing/setting power_default_signal_toggle_rate
|
2019-04-10 20:36:48 -07:00 |
|
James Cherry
|
e5c9bc43fd
|
2.0.10
|
2019-03-12 17:25:53 -07:00 |
|
James Cherry
|
92f4968feb
|
write_path_spice bug fixes
|
2019-01-20 09:44:24 -08:00 |
|
James Cherry
|
b075ccc783
|
update copyright
|
2019-01-01 12:26:11 -08:00 |
|
James Cherry
|
1154fb89fd
|
and then there was light...
|
2018-09-28 08:54:21 -07:00 |