James Cherry
|
ec856896c7
|
verilog read/write to public includes
|
2020-04-05 16:56:38 -07:00 |
|
James Cherry
|
ee326f165c
|
public headers in include/sta
|
2020-04-05 14:53:44 -07:00 |
|
James Cherry
|
804953e317
|
mv public headers to include/sta
|
2020-04-05 11:35:51 -07:00 |
|
James Cherry
|
4a017e86eb
|
update copyright
|
2020-03-06 18:50:37 -08:00 |
|
James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
|
2019-07-03 21:18:38 -07:00 |
|
James Cherry
|
7af69066df
|
VerilogWriter use liberty bus port order
|
2019-07-02 16:33:31 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
d108a15c56
|
write_verilog fails for missing pins
|
2019-06-27 18:04:57 -07:00 |
|
James Cherry
|
5d7ad0a1ef
|
write_verilog use concat for instance bus ports
|
2019-06-27 16:06:46 -07:00 |
|
James Cherry
|
1a84830895
|
sta::worst_slack args, sta to verilog name args
|
2019-06-18 15:52:12 -07:00 |
|
James Cherry
|
eea6ab1a29
|
write_verilog -sorted -> -sort
|
2019-06-17 12:33:37 -07:00 |
|
James Cherry
|
3f7e207491
|
write_verilog
|
2019-06-16 21:08:00 -07:00 |