James Cherry
|
84c13732f7
|
Sta::makeCmdNetwork -> Sta::makeSdcNetwork
|
2019-11-02 19:32:09 -07:00 |
|
James Cherry
|
6ac93c8c7d
|
vertex_pin -> leaf_pin
|
2019-10-25 08:51:59 -07:00 |
|
James Cherry
|
13037e6093
|
rm BugLog
|
2019-10-20 15:28:29 -07:00 |
|
James Cherry
|
56851ed438
|
ssta met/violated include sigma
|
2019-10-09 18:02:54 -10:00 |
|
James Cherry
|
81492652ce
|
create_clock redef preserve propagated
|
2019-10-09 18:02:33 -10:00 |
|
James Cherry
|
0ed0d384ac
|
SwigCleanup use pragmas to disable compile warnings
|
2019-10-09 18:02:02 -10:00 |
|
James Cherry
|
37ee851943
|
sync
|
2019-09-17 17:48:11 -06:00 |
|
James Cherry
|
2bf8b78fa5
|
thread speed
|
2019-09-07 12:37:05 -07:00 |
|
James Cherry
|
f9bc74e962
|
format_distance, area
|
2019-08-16 17:34:48 -07:00 |
|
James Cherry
|
3ae920be7d
|
write_verilog escaped bus name
|
2019-08-13 21:34:35 -07:00 |
|
James Cherry
|
3c67ef972d
|
copyright
|
2019-08-13 21:34:26 -07:00 |
|
James Cherry
|
41ebd34031
|
leaks
|
2019-08-12 22:56:32 -07:00 |
|
James Cherry
|
a20fb113b7
|
gcc compile
|
2019-08-12 21:36:32 -07:00 |
|
James Cherry
|
109925644f
|
regression fast
|
2019-08-09 18:44:31 -07:00 |
|
James Cherry
|
30a5abebc6
|
Hash -> size_t
|
2019-08-08 14:13:02 -07:00 |
|
James Cherry
|
e16696c347
|
wire_load fanout_length values in quotes ucsd20190808
|
2019-08-08 14:12:07 -07:00 |
|
James Cherry
|
73fef1117e
|
copyright
|
2019-07-19 07:27:59 -07:00 |
|
James Cherry
|
ed88ddc292
|
rm DelayFloatClass
|
2019-07-19 07:27:32 -07:00 |
|
James Cherry
|
90be94072b
|
README repo url
|
2019-07-19 07:17:03 -07:00 |
|
James Cherry
|
9d93130ff2
|
range iterators
|
2019-07-18 06:19:00 -07:00 |
|
James Cherry
|
73fb94a2dd
|
set_units
|
2019-07-13 16:56:46 -07:00 |
|
James Cherry
|
fa849908d7
|
set_cmd_units
|
2019-07-08 11:50:41 -07:00 |
|
James Cherry
|
db6b650a52
|
splash include git sha1
|
2019-07-07 09:58:47 -07:00 |
|
James Cherry
|
d7248abcab
|
sdc matches for verilog port nets like \foo[2] [0]
|
2019-07-04 17:26:14 -07:00 |
|
James Cherry
|
74e287a7eb
|
write_verilog escaped bus port name "input [7:0] \in[0] ;"
|
2019-07-03 21:18:38 -07:00 |
|
James Cherry
|
7af69066df
|
VerilogWriter use liberty bus port order
|
2019-07-02 16:33:31 -07:00 |
|
James Cherry
|
eb9fdd1be0
|
write verilog match liberty bus bit order
|
2019-07-02 07:07:34 -07:00 |
|
James Cherry
|
c759feaff6
|
SdcNetwork leak
|
2019-07-01 10:26:59 -07:00 |
|
James Cherry
|
8fa2dd674c
|
SdcNetwork memory error
|
2019-07-01 07:37:52 -07:00 |
|
James Cherry
|
ed6ed7c74b
|
g++ compile issue
|
2019-06-30 22:44:00 -07:00 |
|
James Cherry
|
f34fc4162d
|
base class destructors public virtual or protected non-virtual
|
2019-06-30 22:30:53 -07:00 |
|
James Cherry
|
d76ee0ca62
|
refactor SdcNetwork
|
2019-06-30 17:17:03 -07:00 |
|
James Cherry
|
93f5f9d664
|
no need for virtuals in Concrete network objects
|
2019-06-28 13:38:56 -07:00 |
|
James Cherry
|
88331ab9b1
|
Network bus brkts use library values
|
2019-06-28 11:51:43 -07:00 |
|
James Cherry
|
d108a15c56
|
write_verilog fails for missing pins
|
2019-06-27 18:04:57 -07:00 |
|
James Cherry
|
5d7ad0a1ef
|
write_verilog use concat for instance bus ports
|
2019-06-27 16:06:46 -07:00 |
|
James Cherry
|
61333cd980
|
Network:bus_brkts_left/right
|
2019-06-26 17:14:31 -07:00 |
|
James Cherry
|
344394de29
|
link_design use verilog library to lookup top
|
2019-06-26 16:01:58 -07:00 |
|
James Cherry
|
389b9b8276
|
set_data_check no -setup|-hold
|
2019-06-26 15:58:23 -07:00 |
|
James Cherry
|
beaaafc4f2
|
ChangeLog.txt
|
2019-06-24 17:16:29 -07:00 |
|
James Cherry
|
e05e7185ba
|
report_checks transition_time field -> slew
|
2019-06-24 08:35:04 -07:00 |
|
James Cherry
|
11aa6e759a
|
tclListSeqLibertyCell
|
2019-06-23 21:59:02 -07:00 |
|
James Cherry
|
15e759a992
|
get_lib_cells allow wildcard lib name
|
2019-06-23 21:38:01 -07:00 |
|
James Cherry
|
12494398e9
|
set_clock_sense -> set_sense, LibertyPort::driveResistance
|
2019-06-23 19:52:29 -07:00 |
|
James Cherry
|
b9a7b349eb
|
template tcl typemap(in) seqs/sets
|
2019-06-22 11:17:13 -07:00 |
|
James Cherry
|
78fa68cc7a
|
TclListSeqLibertyLibrary
|
2019-06-21 21:42:45 -07:00 |
|
James Cherry
|
fa680f4500
|
stringBeginEq
|
2019-06-21 13:25:21 -07:00 |
|
James Cherry
|
337fab4c44
|
equiv cells dont_use turd
|
2019-06-21 13:21:37 -07:00 |
|
James Cherry
|
fef70f0983
|
ConcreteNetwork::replaceCell failed if port order differed cont.
|
2019-06-21 12:50:57 -07:00 |
|
James Cherry
|
527b74b8e4
|
ConcreteNetwork::replaceCell failed if port order differed
|
2019-06-21 12:02:35 -07:00 |