3b61817f90
sdc:isConstrained for clk latency pin
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 17:19:23 -07:00
ef924bb0b5
fmt
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 16:41:25 -07:00
b5b0c66d12
power activity doc resolves #192
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 12:37:42 -07:00
60f6e5963f
rm PwrActivityOrigin::defaulted
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 12:21:31 -07:00
bbe31b03de
comment
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 10:58:09 -07:00
ad1cb85580
doc
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-07 09:24:58 -07:00
12c811a492
latch en=1 tags
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-06 18:10:20 -07:00
d8c0e9285b
RiseFall use shortName instead of to_string
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-06 12:02:05 -07:00
f1e5587fef
rapidus liberty latch D->Q/EN->Q matching
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-05 18:41:25 -07:00
8ed837d74b
relevelize latch EN->Q
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-05 13:33:58 -08:00
62cd210a8a
back edge->to is a root resolves #395
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-03 07:59:09 -08:00
eb0446d4e2
Write verilog escape ( #394 )
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* Fir for write_verilog issue 3826
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* staToVerilog2 remove escaped_name+=ch
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* updated regression to remove \ from module name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Using helpers.tcl function to redirect results
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* add std::string and remove trailing space, update regression name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* update regression to reflect correct output verilog name
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
---------
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
2026-03-02 16:48:15 -08:00
73e1a392c5
rm unused Sta::report functions
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-02 16:47:40 -08:00
6f4cdcfea8
tcl sta::is_ideal_clock
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-02 16:41:35 -08:00
f89fcbfa11
tcl sta::is_ideal_clock
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-02 16:26:14 -08:00
e054499e45
report_arrival requires not needed
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-02 13:22:13 -08:00
741bf4d561
rm using std::
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-02 12:13:13 -08:00
94b8fd8f37
dcalc threshold adjustment
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-03-01 17:33:20 -08:00
0f8d7cffd3
mv StdStringSeq defs to StringUtil.hh
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-28 15:53:23 -08:00
e76f54a068
rm TokenParser
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-28 15:45:34 -08:00
cd21c43693
rm LibertyPort::clkTreeDelays, clockTreePathDelays
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-28 14:57:00 -08:00
a6425a3364
FindMessages criticalError
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-28 14:51:09 -08:00
d31372ef9a
regression sta_dir
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-27 17:54:32 -08:00
c010a0f99e
liberty reader rewrite
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-27 17:12:50 -08:00
a47a8dd831
Add GitHub Action for CI and fix broken testcases ( #391 )
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* feat(ci): add GitHub Action for push and pull request
* fix(ci): fix broken testcases
* chore: add CODEOWNERS for ci
* ci: bump actions/upload-artifact from 6 to 7
2026-02-27 13:51:28 -08:00
95d5ebb47c
test/helpers.tcl
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-26 09:32:20 -08:00
a2cd40f57c
fix: Revert "Expose 'TimingType' from `TimingArc`. ( #380 )" ( #390 )
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Now the `TimingArcSet` class in `TimingArc.hh` has two identical declarations of the `timingType()` member function with the same signature, return type and implementation, which causes an overload conflict error during the build process.
This reverts commit f0c9971015
2026-02-25 18:08:47 -08:00
f0c9971015
Expose 'TimingType' from `TimingArc`. ( #380 )
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When using the OpenSTA Liberty file parser as a general-purpose Liberty reader, it's useful to be able to
extract the original `TimingType` for a timing arc, and trivial to support.
2026-02-25 08:13:51 -08:00
d1bfb1df2e
define_scene use filename or library name resolves #386
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-25 07:29:18 -08:00
79ebc3469b
report_path -path_group w/-default resolves openroad issue #9439
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-24 16:45:03 -08:00
795c190edb
ClkLatency::findClkDelays unclocked regs resolves #385
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-24 15:07:33 -08:00
b69645ed44
make_scene missing mode error resolves #384
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-24 14:48:16 -08:00
d19d99dc19
init Parasitics::coupling_cap_factor_ resolves #383
2026-02-17 11:08:29 -07:00
aca993e9ee
Sta::clearNonSdc clear sim resolves #382
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-17 11:03:05 -07:00
54a3cc0721
revert bb23f157
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-13 09:02:22 -07:00
bb23f15732
Sdc::deleteDeratingFactors resolves #381
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-13 08:01:26 -07:00
8925c985b6
Merge branch 'master' into rel_3.0
2026-02-12 08:33:19 -07:00
78bb19c9eb
Report::printToBufferAppend resolves #379
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-12 08:32:45 -07:00
52b49f823f
centos docker
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 12:41:41 -07:00
b92db09fd2
Merge branch 'master' into rel_3.0
2026-02-11 09:23:12 -07:00
506914e0a1
Report::printToBufferAppend resolves #379
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 09:21:50 -07:00
4c157f46ee
InternalPower::related_pg_port string->port
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 08:33:09 -07:00
4689eecacd
clang-format
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 08:12:12 -07:00
4823a4e1e0
Merge branch 'master' into rel_3.0
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 08:11:44 -07:00
f08cdd165a
Power::findLeakagePower
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-11 08:03:34 -07:00
7cb71fe766
liberty memory management
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-04 18:33:32 -07:00
33e480a6c1
liberty memory management
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-04 18:33:04 -07:00
c7f4bb3bb3
Merge branch 'master' into rel_3.0
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-04 17:36:33 -07:00
cde32a1572
leakage power well pg pin resolves #377
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-04 16:50:28 -07:00
98d0f5605e
enable LTO
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Signed-off-by: James Cherry <cherry@parallaxsw.com>
2026-02-03 11:32:15 -07:00
James Cherry
Deepashree Sengupta
Kazuto Iris
Robert O'Callahan