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OpenSTA
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122 Commits

Author SHA1 Message Date
Drew Lewis 424cb1dff1
Add native gzip compression support to write_verilog (#448) 2026-06-10 09:12:19 -07:00
Deepashree Sengupta 5dbc473186
fix makeConcreteParasitics leak+testcase (#439) 
* fix makeConcreteParasitics leak

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* simplify test, update the address review comment

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* reduce test verbosity

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 2026-05-20 13:55:02 -07:00
James Cherry 6eb6911d30 regression 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-05-06 08:51:10 -07:00
James Cherry 6fd319474f regression 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-25 18:59:53 -07:00
James Cherry 15c59e7527 regression.tcl 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-25 16:05:09 -07:00
James Cherry 6bcf7b8156 rm unnecessary sta:: in tcl 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-16 16:12:59 -07:00
Deepashree Sengupta c887b2e4b3
Bias pin handling (#409) 
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 2026-04-07 11:00:01 -07:00
James Cherry 645f2669c9 report_dcalc prima resolves #418 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-07 10:45:04 -07:00
James Cherry 548b665412 get_* -filter allow true/false, '.' in glob pattern resolves #416 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-04 16:19:41 -07:00
James Cherry d6e826ef8b save_ok hook 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-04 14:58:25 -07:00
James Cherry fe23c4530f regression.tcl 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-04-03 16:46:13 -07:00
James Cherry 538db6211f filter_objects via Akash Levy resolves #399 2026-03-30 09:36:21 -07:00
James Cherry 46472e0eed regresssion update failures/diffs 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-29 15:19:00 -07:00
James Cherry f4048cdf3e read_saif ref missing instance resolves #406 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-24 10:31:24 -07:00
James Cherry 7b0281014e regression usage 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-22 10:13:57 -07:00
James Cherry bacb61feaa regression -j 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-03-21 10:18:55 -07:00
Deepashree Sengupta fbe9da3fb7
Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression (#401) 
* Fix for OpenSTA issue 398 and OpenROAD issue 9454 with regression

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Incorporated feedbacks from previous version

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* rename tests

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* remove unnecessary newline

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Updated to use network_->portBitIterator

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 2026-03-10 14:57:21 -07:00
Deepashree Sengupta eb0446d4e2
Write verilog escape (#394) 
* Fir for write_verilog issue 3826

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* staToVerilog2 remove escaped_name+=ch

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* updated regression to remove \ from module name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* Using helpers.tcl function to redirect results

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* add std::string and remove trailing space, update regression name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

* update regression to reflect correct output verilog name

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

---------

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
 2026-03-02 16:48:15 -08:00
James Cherry d31372ef9a regression sta_dir 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-27 17:54:32 -08:00
James Cherry c010a0f99e liberty reader rewrite 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-27 17:12:50 -08:00
Kazuto Iris a47a8dd831
Add GitHub Action for CI and fix broken testcases (#391) 
* feat(ci): add GitHub Action for push and pull request

* fix(ci): fix broken testcases

* chore: add CODEOWNERS for ci

* ci: bump actions/upload-artifact from 6 to 7
 2026-02-27 13:51:28 -08:00
James Cherry 95d5ebb47c test/helpers.tcl 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-02-26 09:32:20 -08:00
James Cherry db01a2122e Merge branch 'master' into rel_3.0 2026-01-23 12:40:57 -07:00
Akash Levy 117e4094bc
Fix for invalid operator error handling (#366) 
* Fix for invalid operator error handling

* Revisions
 2026-01-23 11:39:56 -08:00
James Cherry d42b821c00 rel 3.0 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2026-01-13 09:36:45 -07:00
James Cherry fb61208148 fix and simplify power_json test 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-20 10:45:17 -07:00
nataliakokoromyti 56e4bd8ce1
Report power as JSON (#342) 
* fix power_json.tcl

* get rid of the if/else statements throughout
 2025-12-20 08:13:15 -08:00
James Cherry 323906cb1a prima3 use asap7_small 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-19 09:40:16 -07:00
James Cherry 967f512fdc rename test groups 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 14:47:27 -07:00
James Cherry 75c2b1e80d rm read_vcd test 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 12:53:55 -07:00
James Cherry e09e1b7dcf rm set_units_float test 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-12-05 09:56:14 -07:00
Stan Lee 85b790ce45
Large bus width bug with read_vcd (#348) 
* a

* Revert "a"

This reverts commit 2717585799dc829618bc523a4b1525df2a298cf1.

* bus issue

* reverse string to match vcd bits

* requested changes

* clearer

* this makes more sense

* revert

* comment

* add test case
 2025-12-04 17:04:23 -08:00
Akash Levy 6e16c3f189
Allow `set_units`/`set_cmd_units` to support floats properly (#349) 2025-12-04 08:30:05 -08:00
Akash Levy 16a92707fb
Fix `isBuffer` (#329) 
* Add support for "well" direction type (nwell, pwell, etc.), and fix isBuffer (+ other functions) to accommodate wells

* Just fix isBuffer issue
 2025-11-16 15:34:37 -08:00
James Cherry db3a1dd6e6 disconnect_pin do not delete pin from exceptions 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-13 10:31:43 -07:00
James Cherry 7fab248f56 disconnect_mcp_pin.ok 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-13 10:17:08 -07:00
James Cherry 4dad6ab3b1 disconnect/disconnect pin set_multicycle_path resolves #327 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-13 10:06:57 -07:00
James Cherry 265e7f2d10 get_filter comment 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-11-01 13:25:32 -07:00
James Cherry de0f5440a6 Sta::isPathGroupName 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-10-26 09:23:16 -07:00
ambd161 36e516924f
Recognize some basic specify blocks and ignore them (#309) 
* Add parser support for specify blocks and specparam
Treated like regular parameters, and so ignored

* Add regression test

* Apply PR feedback

* missed the verilog_lang
 2025-10-12 14:11:00 -07:00
Akash Levy 9550c99f0c
Package require test (#303) 2025-10-04 10:36:22 -07:00
Mateusz Gancarz 45a8a1bcc0
search: fix truncating path ends list if sorting by slack (#291) 2025-09-03 16:45:33 -07:00
Akash Levy 4920f673a8
JSON reporting: split out source clock path (#285) 2025-08-13 09:53:44 -07:00
Akash Levy 2e903ab4da
Allow Liberty floats as strings for `voltage_map` and `capacitive_load_unit` (#280) 
* Allow Liberty floats as strings for voltage_map and capacitive_load_unit

* Update liberty_float_as_str.lib

* Use valid bool

* Remove unused include
 2025-08-01 17:41:56 -07:00
Akash Levy ec3208bfbf
Allow backslash-EOL to end tokens in Liberty file (#279) 
* Allow backslash EOL to end tokens in Liberty file

* Update liberty_backslash_eol.lib

* Update liberty_backslash_eol.lib
 2025-07-31 12:19:36 -07:00
Akash Levy c416229106
CMake output lib/exe fixes (#244) 
* Fixes #167

* No need to make app/ directory, it's already there

* Put lib/exe only in build dir, update docs and other references accordingly

* Remove gitignore stuff

* Bump CMake version too

* Minor correction to be more exact

* Update regression_vars.tcl

* Requested txt fixes

* Update date
 2025-05-19 15:04:49 -07:00
James Cherry efee9ec7e4 prima3.ok 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-04-10 11:17:19 -07:00
James Cherry 462853b3b5 regression use include 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-03-31 08:32:25 -07:00
Akash Levy e7e80ca6c2
All path groups (#215) 
* All path groups

* Fixes

* Use c++17 iteration
 2025-02-12 10:40:43 -08:00
James Cherry 2a4fd08211 update copyright 
Signed-off-by: James Cherry <cherry@parallaxsw.com>
 2025-01-21 18:54:33 -07:00