* Implement set_path_margin command
Adds a new set_path_margin SDC command that applies a signed slack
adjustment to the capture-clock side of timing paths. A positive
margin tightens the path (harder to meet) and a negative margin
loosens it. Supports -setup/-hold/-from/-through/-to scoping,
priority/override semantics matching other exceptions, text and
JSON report output, and write_sdc serialisation.
Adapted from Silimate PR #57; uses upstream/master Mode/Scene and
string_view APIs. Test uses unset_path_exceptions in place of the
Silimate-only reset_path alias.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Fix nested delaySum call indentation to match project style.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Address review: store PathMargin on PathEnd, split tests
Keep the path margin exception on PathEndClkConstrained, add
PathEnd::hasPathMargin for report gating, and split the monolithic
regression into set_path_margin1–6. Rebased onto upstream/master and
document the command in ChangeLog.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Document set_path_margin in OpenSTA.fodt/pdf
Add the command reference, index entry, and note that
unset_path_exceptions also clears path margin exceptions.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Drop [[nodiscard]] from PathEnd::hasPathMargin.
Co-authored-by: Cursor <cursoragent@cursor.com>
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Co-authored-by: Cursor <cursoragent@cursor.com>
Use get_port_pin instead of find_pin on the port leaf name so escaped
hierarchical port names like level1/level2/level3 resolve correctly.
Also fix arglilst typo in get_port_pins_error.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Implement set_max_dynamic_power and set_max_leakage_power.
Store max dynamic/leakage power like max area, expose getters through Sta,
write them in write_sdc, and document that they are ignored during timing.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Drop get_max_* Tcl wrappers; use SWIG accessors in tests.
James pointed out the get_max_* commands duplicate existing SWIG
accessors; remove them and call sta::max_* from the regression.
Co-authored-by: Cursor <cursoragent@cursor.com>
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Co-authored-by: Cursor <cursoragent@cursor.com>
* Add read_vcd -begin_time/-end_time activity windowing.
Limit VCD transition and duty counting to an optional time window so
activity annotation can ignore regions outside the interval of interest.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Format VcdCount::setFilter parameters one per line.
Co-authored-by: Cursor <cursoragent@cursor.com>
* Address VCD begin/end review: VcdTime, sentinel, rename.
Use VcdTime and vcd_null_time instead of int64_t/-1, rename
VcdCount filter bounds to begin/end_time, rename the regression to
vcd_begin_end_time, and document read_vcd -begin_time/-end_time in
ChangeLog.txt.
Co-authored-by: Cursor <cursoragent@cursor.com>
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Co-authored-by: Cursor <cursoragent@cursor.com>
Co-authored-by: James Cherry <34749589+jjcherry56@users.noreply.github.com>
* write_path_spice: match side input values to the path arc's transitions
gatePortValues() chose side input values from the first CUDD cube of the
Boolean difference d(f)/d(input), which sensitizes the gate but ignores
the transition directions of the arc the path used:
- For non-unate gates whose Boolean difference is a tautology (xor2,
xnor2) every side variable came back don't-care, and the unknown value
fell through to tie-low in writeSubcktInstVoltSrcs() -- wrong whenever
the path used the when-condition requiring the side high.
- For mux select arcs the cube was an arbitrary data assignment,
unrelated to the output edge the path reported.
Either way the written deck's gate drives the opposite direction from
the reported path: the simulated chain switches with inverted polarity
from that gate onward, edge-qualified arrival measurements fail, and
the deck sums delays from the wrong rise/fall tables.
Constrain the side input condition to the cofactor pair matching this
arc -- f1 & !f0 when the input and driver edges agree (non-inverting),
f0 & !f1 when they differ (inverting) -- threading the gate input
RiseFall from the path stage into gatePortValues(). Also release the
CUDD nodes that were previously leaked (the old code Cudd_Ref'd the
Boolean difference after the generator was freed and never deref'd it).
Fixes#474
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
* test: write_path_spice
arc-sense regression for #474, and outlined in #475
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Co-authored-by: Brian Degnan <bpdegnan@users.noreply.github.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
* support for filter in get_scene/mode
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* extend user defined property to all 10 objects
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* address reviews
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* support for filter in get_scene/mode
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* fix singular G matrix issue for degenerate nets
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* fix the mistake on existing regression- was accidentally modified
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* make changes accounting for future SI support and address reviews
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* simplify comment
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* address feedbacks
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* support for filter in get_scene/mode
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* defineProperty overload
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* define and set user property
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* address review comments to generalize- current support for mode and scene
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* address second round comments- removed user from cmd names
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* remove defaults, check property vals against type defined
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* address reviews, indent
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* indent fix
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* unnecessary space in orig verilog
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
* Update to use well supplies rather than bias pins
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
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Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
Revert error-on-mismatch back to return 1, as the new GitHub Action
(github-actions-are-differences-found) now detects "Differences found"
in CI output, making the error approach unnecessary.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Previously these functions returned 1 on mismatch but no caller
checked the return value, allowing roundtrip failures to go
undetected. Now they call error() so the sta process exits
non-zero and the regression runner catches the failure.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Minju Kim
Akash Levy
dsengupta0628
Brian Degnan
James Cherry
Drew Lewis
James Cherry
Jaehyun Kim
Matt Liberty
Cho Moon