* write_path_spice: match side input values to the path arc's transitions
gatePortValues() chose side input values from the first CUDD cube of the
Boolean difference d(f)/d(input), which sensitizes the gate but ignores
the transition directions of the arc the path used:
- For non-unate gates whose Boolean difference is a tautology (xor2,
xnor2) every side variable came back don't-care, and the unknown value
fell through to tie-low in writeSubcktInstVoltSrcs() -- wrong whenever
the path used the when-condition requiring the side high.
- For mux select arcs the cube was an arbitrary data assignment,
unrelated to the output edge the path reported.
Either way the written deck's gate drives the opposite direction from
the reported path: the simulated chain switches with inverted polarity
from that gate onward, edge-qualified arrival measurements fail, and
the deck sums delays from the wrong rise/fall tables.
Constrain the side input condition to the cofactor pair matching this
arc -- f1 & !f0 when the input and driver edges agree (non-inverting),
f0 & !f1 when they differ (inverting) -- threading the gate input
RiseFall from the path stage into gatePortValues(). Also release the
CUDD nodes that were previously leaked (the old code Cudd_Ref'd the
Boolean difference after the generator was freed and never deref'd it).
Fixes#474
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
* test: write_path_spice
arc-sense regression for #474, and outlined in #475
---------
Co-authored-by: Brian Degnan <bpdegnan@users.noreply.github.com>
Co-authored-by: Claude Fable 5 <noreply@anthropic.com>
Replace removed -spice_directory flag with -spice_file in all 7
spice test scripts to match the upstream API refactoring.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
After merging upstream changes, fix all build errors in C++ test files
and regolden Tcl test golden files to match updated code output.
Build fixes:
- dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use
EXPECT_NEAR for uninitialized subnormal float comparison
- liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed
LibertyBuilder() default constructor in #if 0
- liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder()
call to use sta_->debug()/report(); wrap old visitor tests in #if 0
- search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr
comparison (now returns std::string&)
- search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock
tests to expect throw (API now requires linked network)
Tcl test fixes:
- Remove calls to removed APIs: report_path_end_header/footer, report_path_end2
from 6 search test scripts; regolden their .ok files
- Regolden .ok files for liberty (15), graph (1), network (8),
parasitics (3), sdc (3), util (2), verilog (8) modules to reflect
upstream format changes (timing arcs output, pin ordering, spacing)
All 6103 tests now pass.
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
Update test code to match API changes from upstream master:
- TestGraph.cc: Fix makeScenes() call to pass reference instead of pointer
- TestLibertyClasses.cc: Fix ScaleFactorType wire_res/wire_cap name mapping;
fix TablePtr usage by calling .get() where const TableModel* is expected
- TestLibertyClasses.cc: Update liberty_read_nangate.ok for new timing arc output
- TestPower.cc: Replace PwrActivityOrigin::defaulted with ::unknown;
fix isSet() expectations (unknown origin returns false)
- TestSdcClasses.cc, TestSdf.cc, TestUtil.cc, TestSpice.cc:
Fix RiseFall::to_string() expected values from short form ("^"/"v")
to long form ("rise"/"fall")
- TestUtil.cc: Remove tests for deleted StringVector/split/TokenParser
and StringSet::deleteContents (removed from master)
- TestSpice.cc: Replace StdStringSeq with StringSeq
- helpers.tcl: Use pwd-based result_dir so module tests write results
to their own test/results/ directory
- verilog_bus.ok: Update golden file for new port ordering from master
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>