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write_verilog escape cell names resolves #187 

Signed-off-by: James Cherry <cherry@parallaxsw.com>
This commit is contained in:
James Cherry 2025-01-21 11:00:11 -07:00
parent 17ee13495a
commit fc92c8411d
3 changed files with 12 additions and 3 deletions
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2
include/sta/VerilogNamespace.hh
View File

@ -22,6 +22,8 @@ namespace sta {
using std::string;
string
cellVerilogName(const char *sta_name);
string
instanceVerilogName(const char *sta_name,
const char escape);

6
network/VerilogNamespace.cc
View File

@ -32,6 +32,12 @@ staToVerilog2(const char *sta_name,
static string
verilogToSta(const char *verilog_name);
string
cellVerilogName(const char *sta_name)
{
return staToVerilog(sta_name, '\\');
}
string
instanceVerilogName(const char *sta_name,
const char escape)

7
verilog/VerilogWriter.cc
View File

@ -171,8 +171,8 @@ void
VerilogWriter::writeModule(const Instance *inst)
{
Cell *cell = network_->cell(inst);
fprintf(stream_, "module %s (",
network_->name(cell));
string cell_vname = cellVerilogName(network_->name(cell));
fprintf(stream_, "module %s (", cell_vname.c_str());
writePorts(cell);
writePortDcls(cell);
fprintf(stream_, "\n");
@ -336,8 +336,9 @@ VerilogWriter::writeChild(const Instance *child)
if (!remove_cells_.hasKey(child_cell)) {
const char *child_name = network_->name(child);
string child_vname = instanceVerilogName(child_name, network_->pathEscape());
string child_cell_vname = cellVerilogName(network_->name(child_cell));
fprintf(stream_, " %s %s (",
network_->name(child_cell),
child_cell_vname.c_str(),
child_vname.c_str());
bool first_port = true;
CellPortIterator *port_iter = network_->portIterator(child_cell);