47 lines
1.2 KiB
C++
47 lines
1.2 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2024, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#pragma once
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#include <string>
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namespace sta {
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using std::string;
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string
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cellVerilogName(const char *sta_name);
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string
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instanceVerilogName(const char *sta_name,
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const char escape);
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string
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netVerilogName(const char *sta_name,
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const char escape);
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string
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portVerilogName(const char *sta_name,
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const char escape);
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string
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moduleVerilogToSta(const char *sta_name);
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string
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instanceVerilogToSta(const char *sta_name);
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string
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netVerilogToSta(const char *sta_name);
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string
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portVerilogToSta(const char *sta_name);
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} // namespace
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