diff --git a/include/sta/VerilogNamespace.hh b/include/sta/VerilogNamespace.hh
index 13a8e3a8..c1d7785a 100644
--- a/include/sta/VerilogNamespace.hh
+++ b/include/sta/VerilogNamespace.hh
@@ -22,6 +22,8 @@ namespace sta {
 
 using std::string;
 
+string
+cellVerilogName(const char *sta_name);
 string
 instanceVerilogName(const char *sta_name,
 		    const char escape);
diff --git a/network/VerilogNamespace.cc b/network/VerilogNamespace.cc
index 6d1542b5..a9971637 100644
--- a/network/VerilogNamespace.cc
+++ b/network/VerilogNamespace.cc
@@ -32,6 +32,12 @@ staToVerilog2(const char *sta_name,
 static string
 verilogToSta(const char *verilog_name);
 
+string
+cellVerilogName(const char *sta_name)
+{
+  return staToVerilog(sta_name, '\\');
+}
+
 string
 instanceVerilogName(const char *sta_name,
 		    const char escape)
diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index 9697ba0f..e9d33d6d 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -171,8 +171,8 @@ void
 VerilogWriter::writeModule(const Instance *inst)
 {
   Cell *cell = network_->cell(inst);
-  fprintf(stream_, "module %s (",
-	  network_->name(cell));
+  string cell_vname = cellVerilogName(network_->name(cell));
+  fprintf(stream_, "module %s (", cell_vname.c_str());
   writePorts(cell);
   writePortDcls(cell);
   fprintf(stream_, "\n");
@@ -336,8 +336,9 @@ VerilogWriter::writeChild(const Instance *child)
   if (!remove_cells_.hasKey(child_cell)) {
     const char *child_name = network_->name(child);
     string child_vname = instanceVerilogName(child_name, network_->pathEscape());
+    string child_cell_vname = cellVerilogName(network_->name(child_cell));
     fprintf(stream_, " %s %s (",
-	    network_->name(child_cell),
+	    child_cell_vname.c_str(),
 	    child_vname.c_str());
     bool first_port = true;
     CellPortIterator *port_iter = network_->portIterator(child_cell);