write_verilog escape cell names resolves #187

Signed-off-by: James Cherry <[email protected]>
2026-09-05 00:52:25 +02:00 · 2025-01-21 11:00:11 -07:00
parent 17ee13495a
commit fc92c8411d
3 changed files with 12 additions and 3 deletions
@@ -22,6 +22,8 @@ namespace sta {

 using std::string;

+string
+cellVerilogName(const char *sta_name);
 string
 instanceVerilogName(const char *sta_name,
 		    const char escape);