Merge pull request #64 from akashlevy/master
Create partial set of one-to-one timing arcs for Liberty cell buses when input/output widths are mismatched
This commit is contained in:
James Cherry
GitHub
commit
535c4ea7d3
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@ -2402,23 +2402,34 @@ LibertyReader::makeTimingArcs(const char *from_port_name,
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else {
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// bus -> bus
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if (timing->isOneToOne()) {
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if (static_cast<int>(from_port_iter.size()) == to_port->size()) {
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LibertyPortMemberIterator to_iter(to_port);
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while (from_port_iter.hasNext() && to_iter.hasNext()) {
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LibertyPort *from_port_bit = from_port_iter.next();
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LibertyPort *to_port_bit = to_iter.next();
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if (from_port_bit->direction()->isOutput())
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libWarn(1215, timing->line(), "timing group from output port.");
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builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit,
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related_out_port, timing->attrs(),
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timing->line());
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}
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}
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else
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int from_size = from_port_iter.size();
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int to_size = to_port->size();
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LibertyPortMemberIterator to_port_iter(to_port);
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// warn about different sizes
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if (from_size != to_size)
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libWarn(1216, timing->line(),
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"timing port %s and related port %s are different sizes.",
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from_port_name,
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to_port->name());
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// align to/from iterators for one-to-one mapping
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while (from_size > to_size) {
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from_size--;
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from_port_iter.next();
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}
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while (to_size > from_size) {
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to_size--;
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to_port_iter.next();
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}
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// make timing arcs
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while (from_port_iter.hasNext() && to_port_iter.hasNext()) {
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LibertyPort *from_port_bit = from_port_iter.next();
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LibertyPort *to_port_bit = to_port_iter.next();
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if (from_port_bit->direction()->isOutput())
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libWarn(1215, timing->line(), "timing group from output port.");
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builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit,
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related_out_port, timing->attrs(),
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timing->line());
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}
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}
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else {
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while (from_port_iter.hasNext()) {
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@ -0,0 +1,93 @@
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library (one_to_one_mismatched_width) {
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delay_model : "table_lookup";
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simulation : false;
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capacitive_load_unit (1,pF);
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leakage_power_unit : "1pW";
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current_unit : "1A";
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pulling_resistance_unit : "1kohm";
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time_unit : "1ns";
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voltage_unit : "1v";
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library_features : "report_delay_calculation";
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 30;
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slew_lower_threshold_pct_fall : 30;
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slew_upper_threshold_pct_rise : 70;
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slew_upper_threshold_pct_fall : 70;
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slew_derate_from_library : 1.0;
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nom_process : 1.0;
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nom_temperature : 85.0;
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nom_voltage : 0.75;
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type (bus8) {
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base_type : "array";
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data_type : "bit";
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bit_width : 8;
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bit_from : 7;
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bit_to : 0;
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}
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type (bus4) {
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base_type : "array";
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data_type : "bit";
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bit_width : 4;
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bit_from : 3;
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bit_to : 0;
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}
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cell (inv_8_to_4) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus8";
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direction : "input";
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}
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bus (Y) {
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function : "!A";
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bus_type : "bus4";
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direction : "output";
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timing () {
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related_pin : "A";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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cell (inv_4_to_8) {
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bus (A) {
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capacitance : 1;
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bus_type : "bus4";
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direction : "input";
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}
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bus (Y) {
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function : "!A";
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bus_type : "bus8";
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direction : "output";
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timing () {
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related_pin : "A";
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cell_rise (scalar) {
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values ("1");
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}
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cell_fall (scalar) {
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values ("1");
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}
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rise_transition (scalar) {
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values ("1");
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}
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fall_transition (scalar) {
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values ("1");
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}
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}
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}
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}
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}
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@ -0,0 +1,220 @@
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Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes.
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Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes.
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TEST 1:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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TEST 2:
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Startpoint: a[0] (input port clocked by clk)
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Endpoint: y[0] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[0] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8)
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0.00 1.00 ^ y[0] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[1] (input port clocked by clk)
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Endpoint: y[1] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[1] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8)
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0.00 1.00 ^ y[1] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[2] (input port clocked by clk)
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Endpoint: y[2] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[2] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8)
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0.00 1.00 ^ y[2] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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Startpoint: a[3] (input port clocked by clk)
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Endpoint: y[3] (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v a[3] (in)
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1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8)
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0.00 1.00 ^ y[3] (out)
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1.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 0.00 output external delay
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.00 data arrival time
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---------------------------------------------------------
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-1.00 slack (VIOLATED)
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@ -0,0 +1,17 @@
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read_liberty liberty_arcs_one2one.lib
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puts "TEST 1:"
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read_verilog liberty_arcs_one2one_1.v
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link_design liberty_arcs_one2one_1
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 5
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puts "TEST 2:"
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read_verilog liberty_arcs_one2one_2.v
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link_design liberty_arcs_one2one_2
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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report_checks -group_count 5
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@ -0,0 +1,13 @@
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// Liberty file test: one-to-one mapping with mismatched bit widths
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// Should generate warning but still create timing arcs between bits with same index
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module liberty_arcs_one2one_1 (
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input wire [7:0] a,
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output wire [3:0] y
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);
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inv_8_to_4 partial_wide_inv_cell (
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.A(a),
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.Y(y)
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);
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endmodule
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@ -0,0 +1,13 @@
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// Liberty file test: one-to-one mapping with mismatched bit widths
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// Should generate warning but still create timing arcs between bits with same index
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module liberty_arcs_one2one_2 (
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input wire [3:0] a,
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output wire [7:0] y
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);
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inv_4_to_8 partial_wide_inv_cell (
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.A(a),
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.Y(y)
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);
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endmodule
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@ -124,6 +124,7 @@ record_example_tests {
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record_sta_tests {
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prima3
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verilog_attribute
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liberty_arcs_one2one
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}
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define_test_group fast [group_tests all]
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