From 504ccb97eb489d044a5707fb5832550b101eb492 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 31 Jul 2024 20:48:36 -0700 Subject: [PATCH 1/3] One-to-one mismatched widths: partial timing arc creation --- liberty/LibertyReader.cc | 37 ++++++--- test/one2one.lib | 133 +++++++++++++++++++++++++++++++ test/one2one.ok | 168 +++++++++++++++++++++++++++++++++++++++ test/one2one.tcl | 17 ++++ test/one2one_test1.v | 14 ++++ test/one2one_test2.v | 14 ++++ test/regression_vars.tcl | 1 + 7 files changed, 371 insertions(+), 13 deletions(-) create mode 100644 test/one2one.lib create mode 100644 test/one2one.ok create mode 100644 test/one2one.tcl create mode 100644 test/one2one_test1.v create mode 100644 test/one2one_test2.v diff --git a/liberty/LibertyReader.cc b/liberty/LibertyReader.cc index 1a350d56..5f499842 100644 --- a/liberty/LibertyReader.cc +++ b/liberty/LibertyReader.cc @@ -2402,23 +2402,34 @@ LibertyReader::makeTimingArcs(const char *from_port_name, else { // bus -> bus if (timing->isOneToOne()) { - if (static_cast(from_port_iter.size()) == to_port->size()) { - LibertyPortMemberIterator to_iter(to_port); - while (from_port_iter.hasNext() && to_iter.hasNext()) { - LibertyPort *from_port_bit = from_port_iter.next(); - LibertyPort *to_port_bit = to_iter.next(); - if (from_port_bit->direction()->isOutput()) - libWarn(1215, timing->line(), "timing group from output port."); - builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, - related_out_port, timing->attrs(), - timing->line()); - } - } - else + int from_size = from_port_iter.size(); + int to_size = to_port->size(); + LibertyPortMemberIterator to_port_iter(to_port); + // warn about different sizes + if (from_size != to_size) libWarn(1216, timing->line(), "timing port %s and related port %s are different sizes.", from_port_name, to_port->name()); + // align to/from iterators for one-to-one mapping + while (from_size > to_size) { + from_size--; + from_port_iter.next(); + } + while (to_size > from_size) { + to_size--; + to_port_iter.next(); + } + // make timing arcs + while (from_port_iter.hasNext() && to_port_iter.hasNext()) { + LibertyPort *from_port_bit = from_port_iter.next(); + LibertyPort *to_port_bit = to_port_iter.next(); + if (from_port_bit->direction()->isOutput()) + libWarn(1215, timing->line(), "timing group from output port."); + builder_.makeTimingArcs(cell_, from_port_bit, to_port_bit, + related_out_port, timing->attrs(), + timing->line()); + } } else { while (from_port_iter.hasNext()) { diff --git a/test/one2one.lib b/test/one2one.lib new file mode 100644 index 00000000..124e9f54 --- /dev/null +++ b/test/one2one.lib @@ -0,0 +1,133 @@ +library (one_to_one_mismatched_width_test) { + delay_model : "table_lookup"; + simulation : false; + capacitive_load_unit (1,pF); + leakage_power_unit : "1pW"; + current_unit : "1A"; + pulling_resistance_unit : "1kohm"; + time_unit : "1ns"; + voltage_unit : "1v"; + library_features : "report_delay_calculation"; + input_threshold_pct_rise : 50; + input_threshold_pct_fall : 50; + output_threshold_pct_rise : 50; + output_threshold_pct_fall : 50; + slew_lower_threshold_pct_rise : 30; + slew_lower_threshold_pct_fall : 30; + slew_upper_threshold_pct_rise : 70; + slew_upper_threshold_pct_fall : 70; + slew_derate_from_library : 1.0; + nom_process : 1.0; + nom_temperature : 85.0; + nom_voltage : 0.75; + type (bus20) { + base_type : "array"; + data_type : "bit"; + bit_width : 20; + bit_from : 19; + bit_to : 0; + } + type (bus32) { + base_type : "array"; + data_type : "bit"; + bit_width : 32; + bit_from : 31; + bit_to : 0; + } + + cell (or_32_to_20) { + bus (A) { + capacitance : 1; + bus_type : "bus32"; + direction : "input"; + } + bus (B) { + capacitance : 1; + bus_type : "bus32"; + direction : "input"; + } + bus (Y) { + function : "A | B"; + bus_type : "bus20"; + direction : "output"; + timing () { + related_pin : "A"; + cell_rise (scalar) { + values ("1"); + } + cell_fall (scalar) { + values ("1"); + } + rise_transition (scalar) { + values ("1"); + } + fall_transition (scalar) { + values ("1"); + } + } + timing () { + related_pin : "B"; + cell_rise (scalar) { + values ("1"); + } + cell_fall (scalar) { + values ("1"); + } + rise_transition (scalar) { + values ("1"); + } + fall_transition (scalar) { + values ("1"); + } + } + } + } + + cell (or_20_to_32) { + bus (A) { + capacitance : 1; + bus_type : "bus20"; + direction : "input"; + } + bus (B) { + capacitance : 1; + bus_type : "bus20"; + direction : "input"; + } + bus (Y) { + function : "A | B"; + bus_type : "bus32"; + direction : "output"; + timing () { + related_pin : "A"; + cell_rise (scalar) { + values ("1"); + } + cell_fall (scalar) { + values ("1"); + } + rise_transition (scalar) { + values ("1"); + } + fall_transition (scalar) { + values ("1"); + } + } + timing () { + related_pin : "B"; + cell_rise (scalar) { + values ("1"); + } + cell_fall (scalar) { + values ("1"); + } + rise_transition (scalar) { + values ("1"); + } + fall_transition (scalar) { + values ("1"); + } + } + } + } +} \ No newline at end of file diff --git a/test/one2one.ok b/test/one2one.ok new file mode 100644 index 00000000..a3e1c16d --- /dev/null +++ b/test/one2one.ok @@ -0,0 +1,168 @@ +Warning: one2one.lib line 53, timing port A and related port Y are different sizes. +Warning: one2one.lib line 68, timing port B and related port Y are different sizes. +Warning: one2one.lib line 101, timing port A and related port Y are different sizes. +Warning: one2one.lib line 116, timing port B and related port Y are different sizes. +TEST 1: +Startpoint: a[0] (input port clocked by clk) +Endpoint: y[0] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[0] (in) + 1.00 1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20) + 0.00 1.00 ^ y[0] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[10] (input port clocked by clk) +Endpoint: y[10] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[10] (in) + 1.00 1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20) + 0.00 1.00 ^ y[10] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[11] (input port clocked by clk) +Endpoint: y[11] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[11] (in) + 1.00 1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20) + 0.00 1.00 ^ y[11] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +TEST 2: +Startpoint: a[0] (input port clocked by clk) +Endpoint: y[0] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[0] (in) + 1.00 1.00 ^ wide_or_cell/Y[0] (or_20_to_32) + 0.00 1.00 ^ y[0] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[10] (input port clocked by clk) +Endpoint: y[10] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[10] (in) + 1.00 1.00 ^ wide_or_cell/Y[10] (or_20_to_32) + 0.00 1.00 ^ y[10] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[11] (input port clocked by clk) +Endpoint: y[11] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[11] (in) + 1.00 1.00 ^ wide_or_cell/Y[11] (or_20_to_32) + 0.00 1.00 ^ y[11] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + diff --git a/test/one2one.tcl b/test/one2one.tcl new file mode 100644 index 00000000..1c7e86d3 --- /dev/null +++ b/test/one2one.tcl @@ -0,0 +1,17 @@ +read_liberty one2one.lib + +puts "TEST 1:" +read_verilog one2one_test1.v +link_design one2one_test1 +create_clock -name clk -period 0 +set_input_delay -clock clk 0 [all_inputs] +set_output_delay -clock clk 0 [all_outputs] +report_checks -group_count 3 + +puts "TEST 2:" +read_verilog one2one_test2.v +link_design one2one_test2 +create_clock -name clk -period 0 +set_input_delay -clock clk 0 [all_inputs] +set_output_delay -clock clk 0 [all_outputs] +report_checks -group_count 3 diff --git a/test/one2one_test1.v b/test/one2one_test1.v new file mode 100644 index 00000000..9ba56051 --- /dev/null +++ b/test/one2one_test1.v @@ -0,0 +1,14 @@ +// Liberty file test: one-to-one mapping with mismatched bit widths +// Should generate warning but still create timing arcs between bits with same index +module one2one_test1 ( + input wire [31:0] a, + output wire [19:0] y +); + + or_32_to_20 partial_wide_or_cell ( + .A(a), + .B(32'b0), + .Y(y) + ); + +endmodule \ No newline at end of file diff --git a/test/one2one_test2.v b/test/one2one_test2.v new file mode 100644 index 00000000..b1603e1e --- /dev/null +++ b/test/one2one_test2.v @@ -0,0 +1,14 @@ +// Liberty file test: one-to-one mapping with mismatched bit widths +// Should generate warning but still create timing arcs between bits with same index +module one2one_test2 ( + input wire [19:0] a, + output wire [31:0] y +); + + or_20_to_32 partial_wide_or_cell ( + .A(a), + .B(20'b0), + .Y(y) + ); + +endmodule \ No newline at end of file diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 8fde713d..3297ff54 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -124,6 +124,7 @@ record_example_tests { record_sta_tests { prima3 verilog_attribute + one2one } define_test_group fast [group_tests all] From 17a2a240cc85b14566b78efd89ac00cd42df6477 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Wed, 31 Jul 2024 21:12:00 -0700 Subject: [PATCH 2/3] Improve test case clarity --- test/one2one.lib | 68 ++++++---------------------- test/one2one.ok | 104 ++++++++++++++++++++++++++++++++----------- test/one2one.tcl | 4 +- test/one2one_test1.v | 7 ++- test/one2one_test2.v | 7 ++- 5 files changed, 100 insertions(+), 90 deletions(-) diff --git a/test/one2one.lib b/test/one2one.lib index 124e9f54..5d7136c2 100644 --- a/test/one2one.lib +++ b/test/one2one.lib @@ -20,35 +20,30 @@ library (one_to_one_mismatched_width_test) { nom_process : 1.0; nom_temperature : 85.0; nom_voltage : 0.75; - type (bus20) { + type (bus8) { base_type : "array"; data_type : "bit"; - bit_width : 20; - bit_from : 19; + bit_width : 8; + bit_from : 7; bit_to : 0; } - type (bus32) { + type (bus4) { base_type : "array"; data_type : "bit"; - bit_width : 32; - bit_from : 31; + bit_width : 4; + bit_from : 3; bit_to : 0; } - cell (or_32_to_20) { + cell (inv_8_to_4) { bus (A) { capacitance : 1; - bus_type : "bus32"; - direction : "input"; - } - bus (B) { - capacitance : 1; - bus_type : "bus32"; + bus_type : "bus8"; direction : "input"; } bus (Y) { - function : "A | B"; - bus_type : "bus20"; + function : "!A"; + bus_type : "bus4"; direction : "output"; timing () { related_pin : "A"; @@ -65,38 +60,18 @@ library (one_to_one_mismatched_width_test) { values ("1"); } } - timing () { - related_pin : "B"; - cell_rise (scalar) { - values ("1"); - } - cell_fall (scalar) { - values ("1"); - } - rise_transition (scalar) { - values ("1"); - } - fall_transition (scalar) { - values ("1"); - } - } } } - cell (or_20_to_32) { + cell (inv_4_to_8) { bus (A) { capacitance : 1; - bus_type : "bus20"; - direction : "input"; - } - bus (B) { - capacitance : 1; - bus_type : "bus20"; + bus_type : "bus4"; direction : "input"; } bus (Y) { - function : "A | B"; - bus_type : "bus32"; + function : "!A"; + bus_type : "bus8"; direction : "output"; timing () { related_pin : "A"; @@ -113,21 +88,6 @@ library (one_to_one_mismatched_width_test) { values ("1"); } } - timing () { - related_pin : "B"; - cell_rise (scalar) { - values ("1"); - } - cell_fall (scalar) { - values ("1"); - } - rise_transition (scalar) { - values ("1"); - } - fall_transition (scalar) { - values ("1"); - } - } } } } \ No newline at end of file diff --git a/test/one2one.ok b/test/one2one.ok index a3e1c16d..fba5a1a5 100644 --- a/test/one2one.ok +++ b/test/one2one.ok @@ -1,7 +1,5 @@ -Warning: one2one.lib line 53, timing port A and related port Y are different sizes. -Warning: one2one.lib line 68, timing port B and related port Y are different sizes. -Warning: one2one.lib line 101, timing port A and related port Y are different sizes. -Warning: one2one.lib line 116, timing port B and related port Y are different sizes. +Warning: one2one.lib line 48, timing port A and related port Y are different sizes. +Warning: one2one.lib line 76, timing port A and related port Y are different sizes. TEST 1: Startpoint: a[0] (input port clocked by clk) Endpoint: y[0] (output port clocked by clk) @@ -14,7 +12,7 @@ Path Type: max 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v a[0] (in) - 1.00 1.00 ^ partial_wide_or_cell/Y[0] (or_32_to_20) + 1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_8_to_4) 0.00 1.00 ^ y[0] (out) 1.00 data arrival time @@ -30,8 +28,8 @@ Path Type: max -1.00 slack (VIOLATED) -Startpoint: a[10] (input port clocked by clk) -Endpoint: y[10] (output port clocked by clk) +Startpoint: a[1] (input port clocked by clk) +Endpoint: y[1] (output port clocked by clk) Path Group: clk Path Type: max @@ -40,9 +38,9 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay - 0.00 0.00 v a[10] (in) - 1.00 1.00 ^ partial_wide_or_cell/Y[10] (or_32_to_20) - 0.00 1.00 ^ y[10] (out) + 0.00 0.00 v a[1] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_8_to_4) + 0.00 1.00 ^ y[1] (out) 1.00 data arrival time 0.00 0.00 clock clk (rise edge) @@ -57,8 +55,8 @@ Path Type: max -1.00 slack (VIOLATED) -Startpoint: a[11] (input port clocked by clk) -Endpoint: y[11] (output port clocked by clk) +Startpoint: a[2] (input port clocked by clk) +Endpoint: y[2] (output port clocked by clk) Path Group: clk Path Type: max @@ -67,9 +65,36 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay - 0.00 0.00 v a[11] (in) - 1.00 1.00 ^ partial_wide_or_cell/Y[11] (or_32_to_20) - 0.00 1.00 ^ y[11] (out) + 0.00 0.00 v a[2] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_8_to_4) + 0.00 1.00 ^ y[2] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[3] (input port clocked by clk) +Endpoint: y[3] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[3] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_8_to_4) + 0.00 1.00 ^ y[3] (out) 1.00 data arrival time 0.00 0.00 clock clk (rise edge) @@ -96,7 +121,7 @@ Path Type: max 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay 0.00 0.00 v a[0] (in) - 1.00 1.00 ^ wide_or_cell/Y[0] (or_20_to_32) + 1.00 1.00 ^ partial_wide_inv_cell/Y[0] (inv_4_to_8) 0.00 1.00 ^ y[0] (out) 1.00 data arrival time @@ -112,8 +137,8 @@ Path Type: max -1.00 slack (VIOLATED) -Startpoint: a[10] (input port clocked by clk) -Endpoint: y[10] (output port clocked by clk) +Startpoint: a[1] (input port clocked by clk) +Endpoint: y[1] (output port clocked by clk) Path Group: clk Path Type: max @@ -122,9 +147,9 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay - 0.00 0.00 v a[10] (in) - 1.00 1.00 ^ wide_or_cell/Y[10] (or_20_to_32) - 0.00 1.00 ^ y[10] (out) + 0.00 0.00 v a[1] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[1] (inv_4_to_8) + 0.00 1.00 ^ y[1] (out) 1.00 data arrival time 0.00 0.00 clock clk (rise edge) @@ -139,8 +164,8 @@ Path Type: max -1.00 slack (VIOLATED) -Startpoint: a[11] (input port clocked by clk) -Endpoint: y[11] (output port clocked by clk) +Startpoint: a[2] (input port clocked by clk) +Endpoint: y[2] (output port clocked by clk) Path Group: clk Path Type: max @@ -149,9 +174,36 @@ Path Type: max 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 v input external delay - 0.00 0.00 v a[11] (in) - 1.00 1.00 ^ wide_or_cell/Y[11] (or_20_to_32) - 0.00 1.00 ^ y[11] (out) + 0.00 0.00 v a[2] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[2] (inv_4_to_8) + 0.00 1.00 ^ y[2] (out) + 1.00 data arrival time + + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 clock reconvergence pessimism + 0.00 0.00 output external delay + 0.00 data required time +--------------------------------------------------------- + 0.00 data required time + -1.00 data arrival time +--------------------------------------------------------- + -1.00 slack (VIOLATED) + + +Startpoint: a[3] (input port clocked by clk) +Endpoint: y[3] (output port clocked by clk) +Path Group: clk +Path Type: max + + Delay Time Description +--------------------------------------------------------- + 0.00 0.00 clock clk (rise edge) + 0.00 0.00 clock network delay (ideal) + 0.00 0.00 v input external delay + 0.00 0.00 v a[3] (in) + 1.00 1.00 ^ partial_wide_inv_cell/Y[3] (inv_4_to_8) + 0.00 1.00 ^ y[3] (out) 1.00 data arrival time 0.00 0.00 clock clk (rise edge) diff --git a/test/one2one.tcl b/test/one2one.tcl index 1c7e86d3..a53ba830 100644 --- a/test/one2one.tcl +++ b/test/one2one.tcl @@ -6,7 +6,7 @@ link_design one2one_test1 create_clock -name clk -period 0 set_input_delay -clock clk 0 [all_inputs] set_output_delay -clock clk 0 [all_outputs] -report_checks -group_count 3 +report_checks -group_count 5 puts "TEST 2:" read_verilog one2one_test2.v @@ -14,4 +14,4 @@ link_design one2one_test2 create_clock -name clk -period 0 set_input_delay -clock clk 0 [all_inputs] set_output_delay -clock clk 0 [all_outputs] -report_checks -group_count 3 +report_checks -group_count 5 diff --git a/test/one2one_test1.v b/test/one2one_test1.v index 9ba56051..a3365891 100644 --- a/test/one2one_test1.v +++ b/test/one2one_test1.v @@ -1,13 +1,12 @@ // Liberty file test: one-to-one mapping with mismatched bit widths // Should generate warning but still create timing arcs between bits with same index module one2one_test1 ( - input wire [31:0] a, - output wire [19:0] y + input wire [7:0] a, + output wire [3:0] y ); - or_32_to_20 partial_wide_or_cell ( + inv_8_to_4 partial_wide_inv_cell ( .A(a), - .B(32'b0), .Y(y) ); diff --git a/test/one2one_test2.v b/test/one2one_test2.v index b1603e1e..8f208be4 100644 --- a/test/one2one_test2.v +++ b/test/one2one_test2.v @@ -1,13 +1,12 @@ // Liberty file test: one-to-one mapping with mismatched bit widths // Should generate warning but still create timing arcs between bits with same index module one2one_test2 ( - input wire [19:0] a, - output wire [31:0] y + input wire [3:0] a, + output wire [7:0] y ); - or_20_to_32 partial_wide_or_cell ( + inv_4_to_8 partial_wide_inv_cell ( .A(a), - .B(20'b0), .Y(y) ); From f5284ca53d8670a411b80fe288bc37921e8231ec Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 1 Aug 2024 21:14:48 -0700 Subject: [PATCH 3/3] Rename files as requested --- test/{one2one.lib => liberty_arcs_one2one.lib} | 2 +- test/{one2one.ok => liberty_arcs_one2one.ok} | 4 ++-- test/{one2one.tcl => liberty_arcs_one2one.tcl} | 10 +++++----- test/{one2one_test1.v => liberty_arcs_one2one_1.v} | 2 +- test/{one2one_test2.v => liberty_arcs_one2one_2.v} | 2 +- test/regression_vars.tcl | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) rename test/{one2one.lib => liberty_arcs_one2one.lib} (97%) rename test/{one2one.ok => liberty_arcs_one2one.ok} (97%) rename test/{one2one.tcl => liberty_arcs_one2one.tcl} (64%) rename test/{one2one_test1.v => liberty_arcs_one2one_1.v} (86%) rename test/{one2one_test2.v => liberty_arcs_one2one_2.v} (86%) diff --git a/test/one2one.lib b/test/liberty_arcs_one2one.lib similarity index 97% rename from test/one2one.lib rename to test/liberty_arcs_one2one.lib index 5d7136c2..7eebe107 100644 --- a/test/one2one.lib +++ b/test/liberty_arcs_one2one.lib @@ -1,4 +1,4 @@ -library (one_to_one_mismatched_width_test) { +library (one_to_one_mismatched_width) { delay_model : "table_lookup"; simulation : false; capacitive_load_unit (1,pF); diff --git a/test/one2one.ok b/test/liberty_arcs_one2one.ok similarity index 97% rename from test/one2one.ok rename to test/liberty_arcs_one2one.ok index fba5a1a5..22d298ef 100644 --- a/test/one2one.ok +++ b/test/liberty_arcs_one2one.ok @@ -1,5 +1,5 @@ -Warning: one2one.lib line 48, timing port A and related port Y are different sizes. -Warning: one2one.lib line 76, timing port A and related port Y are different sizes. +Warning: liberty_arcs_one2one.lib line 48, timing port A and related port Y are different sizes. +Warning: liberty_arcs_one2one.lib line 76, timing port A and related port Y are different sizes. TEST 1: Startpoint: a[0] (input port clocked by clk) Endpoint: y[0] (output port clocked by clk) diff --git a/test/one2one.tcl b/test/liberty_arcs_one2one.tcl similarity index 64% rename from test/one2one.tcl rename to test/liberty_arcs_one2one.tcl index a53ba830..38bac255 100644 --- a/test/one2one.tcl +++ b/test/liberty_arcs_one2one.tcl @@ -1,16 +1,16 @@ -read_liberty one2one.lib +read_liberty liberty_arcs_one2one.lib puts "TEST 1:" -read_verilog one2one_test1.v -link_design one2one_test1 +read_verilog liberty_arcs_one2one_1.v +link_design liberty_arcs_one2one_1 create_clock -name clk -period 0 set_input_delay -clock clk 0 [all_inputs] set_output_delay -clock clk 0 [all_outputs] report_checks -group_count 5 puts "TEST 2:" -read_verilog one2one_test2.v -link_design one2one_test2 +read_verilog liberty_arcs_one2one_2.v +link_design liberty_arcs_one2one_2 create_clock -name clk -period 0 set_input_delay -clock clk 0 [all_inputs] set_output_delay -clock clk 0 [all_outputs] diff --git a/test/one2one_test1.v b/test/liberty_arcs_one2one_1.v similarity index 86% rename from test/one2one_test1.v rename to test/liberty_arcs_one2one_1.v index a3365891..46d11e2a 100644 --- a/test/one2one_test1.v +++ b/test/liberty_arcs_one2one_1.v @@ -1,6 +1,6 @@ // Liberty file test: one-to-one mapping with mismatched bit widths // Should generate warning but still create timing arcs between bits with same index -module one2one_test1 ( +module liberty_arcs_one2one_1 ( input wire [7:0] a, output wire [3:0] y ); diff --git a/test/one2one_test2.v b/test/liberty_arcs_one2one_2.v similarity index 86% rename from test/one2one_test2.v rename to test/liberty_arcs_one2one_2.v index 8f208be4..8bc66fad 100644 --- a/test/one2one_test2.v +++ b/test/liberty_arcs_one2one_2.v @@ -1,6 +1,6 @@ // Liberty file test: one-to-one mapping with mismatched bit widths // Should generate warning but still create timing arcs between bits with same index -module one2one_test2 ( +module liberty_arcs_one2one_2 ( input wire [3:0] a, output wire [7:0] y ); diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 3297ff54..5ecca193 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -124,7 +124,7 @@ record_example_tests { record_sta_tests { prima3 verilog_attribute - one2one + liberty_arcs_one2one } define_test_group fast [group_tests all]