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This commit is contained in:
James Cherry
2020-07-03 18:20:20 -07:00
parent 535a09edcc e7ed3170f3
commit 47bb1e124f
1 changed files with 11 additions and 3 deletions
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verilog/VerilogWriter.cc
+11 -3
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@@ -165,12 +165,20 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
return "input";
else if (dir == PortDirection::output())
return "output";
else if (dir == PortDirection::bidirect())
return "inout";
else if (dir == PortDirection::tristate())
return "output";
else
else if (dir == PortDirection::bidirect())
return "inout";
else if (dir == PortDirection::power())
return "input";
else if (dir == PortDirection::ground())
return "input";
else if (dir == PortDirection::internal())
return nullptr;
else {
internalError("unknown port direction");
return nullptr;
}
}
void