From e7ed3170f32c8a52961a3ee2290afec5294b90f8 Mon Sep 17 00:00:00 2001
From: James Cherry <cherry@parallaxsw.com>
Date: Fri, 3 Jul 2020 16:56:15 -0700
Subject: [PATCH] write_verilog power/ground port dcls

---
 verilog/VerilogWriter.cc | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/verilog/VerilogWriter.cc b/verilog/VerilogWriter.cc
index 52ffc0f4..ed475971 100644
--- a/verilog/VerilogWriter.cc
+++ b/verilog/VerilogWriter.cc
@@ -165,12 +165,20 @@ VerilogWriter::verilogPortDir(PortDirection *dir)
     return "input";
   else if (dir == PortDirection::output())
     return "output";
-  else if (dir == PortDirection::bidirect())
-    return "inout";
   else if (dir == PortDirection::tristate())
     return "output";
-  else
+  else if (dir == PortDirection::bidirect())
+    return "inout";
+  else if (dir == PortDirection::power())
+    return "input";
+  else if (dir == PortDirection::ground())
+    return "input";
+  else if (dir == PortDirection::internal())
     return nullptr;
+  else {
+    internalError("unknown port direction");
+    return nullptr;
+  }
 }
 
 void