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make_net check for existing

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Signed-off-by: James Cherry <[email protected]>
This commit is contained in:
James Cherry
2026-06-24 18:02:47 -07:00
parent 7527553111
commit 2f26c1e21a
2 changed files with 12 additions and 9 deletions
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search/Sta.cc
+9 -3
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@@ -4407,9 +4407,15 @@ Sta::makeNet(const char *name,
{
NetworkEdit *network = networkCmdEdit();
std::string escaped = escapeBrackets(name, network);
Net *net = network->makeNet(escaped, parent);
// Sta notification unnecessary.
return net;
if (network->findNet(parent, escaped)) {
report_->warn(1557, "net {} already exists.", name);
return nullptr;
}
else {
Net *net = network->makeNet(escaped, parent);
// Sta notification unnecessary.
return net;
}
}
void
verilog/VerilogReader.cc
+3 -6
View File
@@ -1468,8 +1468,7 @@ VerilogReader::linkNetwork(std::string_view top_cell_name,
while (net_name_iter->hasNext()) {
const std::string &net_name = net_name_iter->next();
Port *port = network_->findPort(top_cell, net_name);
Net *net =
bindings.ensureNetBinding(net_name, top_instance, network_);
Net *net = bindings.ensureNetBinding(net_name, top_instance, network_);
// Guard against repeated port name.
if (network_->findPin(top_instance, port) == nullptr) {
Pin *pin = network_->makePin(top_instance, port, nullptr);
@@ -1521,13 +1520,11 @@ VerilogReader::makeModuleInstBody(VerilogModule *module,
if (assign)
mergeAssignNet(assign, module, inst, bindings);
if (dir->isGround()) {
Net *net =
bindings->ensureNetBinding(arg->netName(), inst, network_);
Net *net = bindings->ensureNetBinding(arg->netName(), inst, network_);
network_->addConstantNet(net, LogicValue::zero);
}
if (dir->isPower()) {
Net *net =
bindings->ensureNetBinding(arg->netName(), inst, network_);
Net *net = bindings->ensureNetBinding(arg->netName(), inst, network_);
network_->addConstantNet(net, LogicValue::one);
}
}