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Merge remote-tracking branch 'cherry/master' into update 

Signed-off-by: Matt Liberty <mliberty@precisioninno.com>
This commit is contained in:
Matt Liberty 2023-10-17 16:01:52 -07:00
parent 44f06c5215 fa65070682
commit 1fed0491bb
12 changed files with 89 additions and 90 deletions
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6
README.md
View File

@ -68,11 +68,7 @@ Removing copyright and license notices from OpenSTA sources (or any
other open source project for that matter) is illegal. This should be
obvious, but the author of OpenSTA has discovered two different cases
where the copyright and license were removed from source files that
were copied. The Chinese iEDA project from the Peng Cheng Laboratory
of the Institute of Computing Technology, Chinese Academy of Sciences
is one example. The iEDA project copied multiple OpenSTA files and
removed both the license and copyright notices, replacing them with
their own copyright and license.
were copied.
The official git repository is located at
https://github.com/parallaxsw/OpenSTA.git. Any forks from this code

46
dcalc/GraphDelayCalc1.cc
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@ -170,7 +170,7 @@ MultiDrvrNet::netCaps(const RiseFall *drvr_rf,
pin_cap = net_caps.pinCap();
wire_cap = net_caps.wireCap();
fanout = net_caps.fanout();
has_net_load = net_caps.hasSetLoad();
has_net_load = net_caps.hasNetLoad();
}
void
@ -577,27 +577,27 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex,
Port *port = network_->port(drvr_pin);
drive = sdc_->findInputDrive(port);
}
for (auto tr : RiseFall::range()) {
for (auto rf : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
if (drive) {
const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
const LibertyCell *drvr_cell;
const LibertyPort *from_port, *to_port;
float *from_slews;
drive->driveCell(tr, cnst_min_max, drvr_cell, from_port,
drive->driveCell(rf, cnst_min_max, drvr_cell, from_port,
from_slews, to_port);
if (drvr_cell) {
if (from_port == nullptr)
from_port = driveCellDefaultFromPort(drvr_cell, to_port);
findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, tr,
findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, rf,
from_port, from_slews, to_port, dcalc_ap);
}
else
seedNoDrvrCellSlew(drvr_vertex, drvr_pin, tr, drive, dcalc_ap,
seedNoDrvrCellSlew(drvr_vertex, drvr_pin, rf, drive, dcalc_ap,
arc_delay_calc);
}
else
seedNoDrvrSlew(drvr_vertex, drvr_pin, tr, dcalc_ap, arc_delay_calc);
seedNoDrvrSlew(drvr_vertex, drvr_pin, rf, dcalc_ap, arc_delay_calc);
}
}
}
@ -679,23 +679,23 @@ GraphDelayCalc1::seedLoadSlew(Vertex *vertex)
vertex->name(sdc_network_));
ClockSet *clks = sdc_->findLeafPinClocks(pin);
initSlew(vertex);
for (auto tr : RiseFall::range()) {
for (auto rf : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (!vertex->slewAnnotated(tr, slew_min_max)) {
if (!vertex->slewAnnotated(rf, slew_min_max)) {
float slew = 0.0;
if (clks) {
slew = slew_min_max->initValue();
ClockSet::Iterator clk_iter(clks);
while (clk_iter.hasNext()) {
Clock *clk = clk_iter.next();
float clk_slew = clk->slew(tr, slew_min_max);
float clk_slew = clk->slew(rf, slew_min_max);
if (slew_min_max->compare(clk_slew, slew))
slew = clk_slew;
}
}
DcalcAPIndex ap_index = dcalc_ap->index();
graph_->setSlew(vertex, tr, ap_index, slew);
graph_->setSlew(vertex, rf, ap_index, slew);
}
}
}
@ -963,9 +963,9 @@ GraphDelayCalc1::initRootSlews(Vertex *vertex)
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
DcalcAPIndex ap_index = dcalc_ap->index();
for (auto tr : RiseFall::range()) {
if (!vertex->slewAnnotated(tr, slew_min_max))
graph_->setSlew(vertex, tr, ap_index, default_slew);
for (auto rf : RiseFall::range()) {
if (!vertex->slewAnnotated(rf, slew_min_max))
graph_->setSlew(vertex, rf, ap_index, default_slew);
}
}
}
@ -1161,12 +1161,12 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin,
void
GraphDelayCalc1::initSlew(Vertex *vertex)
{
for (auto tr : RiseFall::range()) {
for (auto rf : RiseFall::range()) {
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
if (!vertex->slewAnnotated(tr, slew_min_max)) {
if (!vertex->slewAnnotated(rf, slew_min_max)) {
DcalcAPIndex ap_index = dcalc_ap->index();
graph_->setSlew(vertex, tr, ap_index, slew_min_max->initValue());
graph_->setSlew(vertex, rf, ap_index, slew_min_max->initValue());
}
}
}
@ -1178,11 +1178,11 @@ GraphDelayCalc1::zeroSlewAndWireDelays(Vertex *drvr_vertex)
for (auto dcalc_ap : corners_->dcalcAnalysisPts()) {
DcalcAPIndex ap_index = dcalc_ap->index();
const MinMax *slew_min_max = dcalc_ap->slewMinMax();
for (auto tr : RiseFall::range()) {
for (auto rf : RiseFall::range()) {
// Init drvr slew.
if (!drvr_vertex->slewAnnotated(tr, slew_min_max)) {
if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) {
DcalcAPIndex ap_index = dcalc_ap->index();
graph_->setSlew(drvr_vertex, tr, ap_index, slew_min_max->initValue());
graph_->setSlew(drvr_vertex, rf, ap_index, slew_min_max->initValue());
}
// Init wire delays and slews.
@ -1191,11 +1191,11 @@ GraphDelayCalc1::zeroSlewAndWireDelays(Vertex *drvr_vertex)
Edge *wire_edge = edge_iter.next();
if (wire_edge->isWire()) {
Vertex *load_vertex = wire_edge->to(graph_);
if (!graph_->wireDelayAnnotated(wire_edge, tr, ap_index))
graph_->setWireArcDelay(wire_edge, tr, ap_index, 0.0);
if (!graph_->wireDelayAnnotated(wire_edge, rf, ap_index))
graph_->setWireArcDelay(wire_edge, rf, ap_index, 0.0);
// Init load vertex slew.
if (!load_vertex->slewAnnotated(tr, slew_min_max))
graph_->setSlew(load_vertex, tr, ap_index, 0.0);
if (!load_vertex->slewAnnotated(rf, slew_min_max))
graph_->setSlew(load_vertex, rf, ap_index, 0.0);
}
}
}

8
dcalc/NetCaps.cc
View File

@ -25,11 +25,11 @@ NetCaps::NetCaps()
NetCaps::NetCaps(float pin_cap,
float wire_cap,
float fanout,
bool has_set_load) :
bool has_net_load) :
pin_cap_(pin_cap),
wire_cap_(wire_cap),
fanout_(fanout),
has_set_load_(has_set_load)
has_net_load_(has_net_load)
{
}
@ -37,12 +37,12 @@ void
NetCaps::init(float pin_cap,
float wire_cap,
float fanout,
bool has_set_load)
bool has_net_load)
{
pin_cap_ = pin_cap;
wire_cap_ = wire_cap;
fanout_ = fanout;
has_set_load_ = has_set_load;
has_net_load_ = has_net_load;
}
} // namespace

8
dcalc/NetCaps.hh
View File

@ -26,21 +26,21 @@ public:
NetCaps(float pin_cap,
float wire_cap,
float fanout,
bool has_set_load);
bool has_net_load);
void init(float pin_cap,
float wire_cap,
float fanout,
bool has_set_load);
bool has_net_load);
float pinCap() const { return pin_cap_; }
float wireCap() const{ return wire_cap_; }
float fanout() const{ return fanout_; }
bool hasSetLoad() const { return has_set_load_; }
bool hasNetLoad() const { return has_net_load_; }
private:
float pin_cap_;
float wire_cap_;
float fanout_;
bool has_set_load_;
bool has_net_load_;
};
} // namespace

1
include/sta/StringUtil.hh
View File

@ -148,7 +148,6 @@ stringDeleteCheck(const char *str);
inline void
stringDelete(const char *str)
{
stringDeleteCheck(str);
delete [] str;
}

2
network/Network.cc
View File

@ -1981,7 +1981,7 @@ CellIdLess::CellIdLess(const Network *network) :
bool
CellIdLess::operator()(const Cell *cell1,
const Cell *cell2) const
const Cell *cell2) const
{
return network_->id(cell1) < network_->id(cell2);
}

3
power/Power.cc
View File

@ -219,7 +219,8 @@ Power::power(const Corner *corner,
if (cell) {
PowerResult inst_power = power(inst, cell, corner);
if (cell->isMacro()
|| cell->isMemory())
|| cell->isMemory()
|| cell->interfaceTiming())
macro.incr(inst_power);
else if (cell->isPad())
pad.incr(inst_power);

52
power/ReadVcdActivities.cc
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@ -131,36 +131,42 @@ ReadVcdActivities::setVarActivity(VcdVar *var,
string &var_name,
const VcdValues &var_values)
{
string sta_name = netVerilogToSta(var_name.c_str());
if (var->width() == 1)
if (var->width() == 1) {
string sta_name = netVerilogToSta(var_name.c_str());
setVarActivity(sta_name.c_str(), var_values, 0);
}
else {
bool is_bus, is_range, subscript_wild;
string bus_name;
int from, to;
parseBusName(sta_name.c_str(), '[', ']', '\\',
parseBusName(var_name.c_str(), '[', ']', '\\',
is_bus, is_range, bus_name, from, to, subscript_wild);
int value_bit = 0;
if (to < from) {
for (int bus_bit = to; bus_bit <= from; bus_bit++) {
string pin_name = bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += ']';
setVarActivity(pin_name.c_str(), var_values, value_bit);
value_bit++;
}
}
else {
for (int bus_bit = to; bus_bit >= from; bus_bit--) {
string pin_name = bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += ']';
setVarActivity(pin_name.c_str(), var_values, value_bit);
value_bit++;
if (is_bus) {
string sta_bus_name = netVerilogToSta(bus_name.c_str());
int value_bit = 0;
if (to < from) {
for (int bus_bit = to; bus_bit <= from; bus_bit++) {
string pin_name = sta_bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += ']';
setVarActivity(pin_name.c_str(), var_values, value_bit);
value_bit++;
}
}
else {
for (int bus_bit = to; bus_bit >= from; bus_bit--) {
string pin_name = sta_bus_name;
pin_name += '[';
pin_name += to_string(bus_bit);
pin_name += ']';
setVarActivity(pin_name.c_str(), var_values, value_bit);
value_bit++;
}
}
}
else
report_->warn(807, "problem parsing bus %s.", var_name.c_str());
}
}
@ -185,8 +191,6 @@ ReadVcdActivities::setVarActivity(const char *pin_name,
else {
power_->setUserActivity(pin, activity, duty,
PwrActivityOrigin::user);
if (annotated_pins_.hasKey(pin))
printf("luse\n");
annotated_pins_.insert(pin);
}
}

8
power/VcdReader.cc
View File

@ -194,7 +194,7 @@ VcdReader::parseVar()
type_name.c_str());
else {
int width = stoi(tokens[1]);
string id = tokens[2];
string &id = tokens[2];
string name;
for (string &context : scope_) {
@ -203,8 +203,12 @@ VcdReader::parseVar()
}
name += tokens[3];
// iverilog separates bus base name from bit range.
if (tokens.size() == 5)
if (tokens.size() == 5) {
// Preserve space after esacaped name.
if (name[0] == '\\')
name += ' ';
name += tokens[4];
}
vcd_->makeVar(name, type, width, id);
}

11
sdc/Sdc.cc
View File

@ -3050,9 +3050,11 @@ Sdc::drvrPinWireCap(const Pin *pin,
{
MinMaxFloatValues *values = drvr_pin_wire_cap_maps_[corner->index()].findKey(pin);
if (values)
return values->value(min_max, cap, exists);
cap = 0.0;
exists = false;
values->value(min_max, cap, exists);
else {
cap = 0.0;
exists = false;
}
}
void
@ -3119,9 +3121,8 @@ Sdc::connectedCap(const Pin *pin,
pin_cap, wire_cap, fanout, has_net_load);
float net_wire_cap;
drvrPinWireCap(pin, corner, min_max, net_wire_cap, has_net_load);
if (has_net_load) {
if (has_net_load)
wire_cap += net_wire_cap;
}
}
float

18
search/ClkSkew.cc
View File

@ -370,14 +370,16 @@ ClkSkews::findClkDelays(const Clock *clk,
while (path_iter.hasNext()) {
PathVertex *path = path_iter.next();
const ClockEdge *path_clk_edge = path->clkEdge(this);
const RiseFall *clk_rf = path_clk_edge->transition();
const Clock *path_clk = path_clk_edge->clock();
if (path_clk == clk) {
Arrival arrival = path->arrival(this);
Delay clk_delay = delayAsFloat(arrival) - path_clk_edge->time();
const MinMax *min_max = path->minMax(this);
const RiseFall *rf = path->transition(this);
delays[clk_rf->index()][rf->index()].setValue(min_max, clk_delay);
if (path_clk_edge) {
const RiseFall *clk_rf = path_clk_edge->transition();
const Clock *path_clk = path_clk_edge->clock();
if (path_clk == clk) {
Arrival arrival = path->arrival(this);
Delay clk_delay = delayAsFloat(arrival) - path_clk_edge->time();
const MinMax *min_max = path->minMax(this);
const RiseFall *rf = path->transition(this);
delays[clk_rf->index()][rf->index()].setValue(min_max, clk_delay);
}
}
}
}

16
search/Corner.cc
View File

@ -105,8 +105,7 @@ Corners::copy(Corners *corners)
clear();
int index = 0;
for (Corner *orig : corners->corners_) {
const char *name = orig->name();
Corner *corner = new Corner(name, index);
Corner *corner = new Corner(orig->name(), index);
corners_.push_back(corner);
// Use the copied name in the map.
corner_map_[corner->name()] = corner;
@ -120,17 +119,10 @@ Corners::copy(Corners *corners)
parasitic_analysis_pts_.push_back(ap);
}
int i = 0;
for (Corner *orig : corners->corners_) {
for (size_t i = 0; i < corners->corners_.size(); i++) {
Corner *orig = corners->corners_[i];
Corner *corner = corners_[i];
auto &orig_aps = orig->parasitic_analysis_pts_;
auto &corner_aps = corner->parasitic_analysis_pts_;
corner_aps.resize(orig_aps.size());
for (ParasiticAnalysisPt *orig_ap : orig_aps) {
int ap_index = orig_ap->index();
corner_aps.push_back(parasitic_analysis_pts_[ap_index]);
}
i++;
corner->parasitic_analysis_pts_ = orig->parasitic_analysis_pts_;
}
}