commit
44f06c5215
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@ -515,14 +515,14 @@ MakeTimingModel::findClkInsertionDelays()
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{
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Instance *top_inst = network_->topInstance();
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Cell *top_cell = network_->cell(top_inst);
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CellPortIterator *port_iter = network_->portIterator(top_cell);
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CellPortIterator *port_iter = network_->portBitIterator(top_cell);
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while (port_iter->hasNext()) {
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Port *port = port_iter->next();
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if (network_->direction(port)->isInput()) {
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const char *port_name = network_->name(port);
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LibertyPort *lib_port = cell_->findLibertyPort(port_name);
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Pin *pin = network_->findPin(top_inst, port);
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if (sdc_->isClock(pin)) {
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if (pin && sdc_->isClock(pin)) {
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lib_port->setIsClock(true);
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ClockSet *clks = sdc_->findClocks(pin);
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size_t clk_count = clks->size();
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17
tcl/StaTcl.i
17
tcl/StaTcl.i
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@ -6032,15 +6032,15 @@ requireds_clk(const RiseFall *rf,
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const RiseFall *clk_rf)
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{
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Sta *sta = Sta::sta();
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FloatSeq requireds;
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FloatSeq reqs;
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const ClockEdge *clk_edge = nullptr;
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if (clk)
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clk_edge = clk->edge(clk_rf);
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for (auto path_ap : sta->corners()->pathAnalysisPts()) {
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requireds.push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge,
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path_ap)));
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reqs.push_back(delayAsFloat(sta->vertexRequired(self, rf, clk_edge,
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path_ap)));
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}
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return requireds;
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return reqs;
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}
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StringSeq
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@ -6050,16 +6050,15 @@ requireds_clk_delays(const RiseFall *rf,
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int digits)
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{
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Sta *sta = Sta::sta();
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StringSeq requireds;
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StringSeq reqs;
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const ClockEdge *clk_edge = nullptr;
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if (clk)
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clk_edge = clk->edge(clk_rf);
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for (auto path_ap : sta->corners()->pathAnalysisPts()) {
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requireds.push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge,
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path_ap),
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sta, digits));
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reqs.push_back(delayAsString(sta->vertexRequired(self, rf, clk_edge, path_ap),
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sta, digits));
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}
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return requireds;
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return reqs;
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}
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Slack
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