From 276af3ddbb572576bd8486fc5bf0055e370b2ff3 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 10 Oct 2023 16:01:02 -0700 Subject: [PATCH 1/8] readme Signed-off-by: James Cherry --- README.md | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/README.md b/README.md index f8687132..3c6bd4b0 100644 --- a/README.md +++ b/README.md @@ -68,11 +68,7 @@ Removing copyright and license notices from OpenSTA sources (or any other open source project for that matter) is illegal. This should be obvious, but the author of OpenSTA has discovered two different cases where the copyright and license were removed from source files that -were copied. The Chinese iEDA project from the Peng Cheng Laboratory -of the Institute of Computing Technology, Chinese Academy of Sciences -is one example. The iEDA project copied multiple OpenSTA files and -removed both the license and copyright notices, replacing them with -their own copyright and license. +were copied. The official git repository is located at https://github.com/parallaxsw/OpenSTA.git. Any forks from this code From 239e6f0319f1c3f60aa4ac9655ccae3acd39aace Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 11 Oct 2023 13:28:53 -0700 Subject: [PATCH 2/8] NetCaps has_set_load -> has_net_load Signed-off-by: James Cherry --- dcalc/GraphDelayCalc1.cc | 2 +- dcalc/NetCaps.cc | 8 ++++---- dcalc/NetCaps.hh | 8 ++++---- sdc/Sdc.cc | 8 +++++--- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/dcalc/GraphDelayCalc1.cc b/dcalc/GraphDelayCalc1.cc index 4ddbe053..a238242a 100644 --- a/dcalc/GraphDelayCalc1.cc +++ b/dcalc/GraphDelayCalc1.cc @@ -170,7 +170,7 @@ MultiDrvrNet::netCaps(const RiseFall *drvr_rf, pin_cap = net_caps.pinCap(); wire_cap = net_caps.wireCap(); fanout = net_caps.fanout(); - has_net_load = net_caps.hasSetLoad(); + has_net_load = net_caps.hasNetLoad(); } void diff --git a/dcalc/NetCaps.cc b/dcalc/NetCaps.cc index d0fb1eb8..4521eb99 100644 --- a/dcalc/NetCaps.cc +++ b/dcalc/NetCaps.cc @@ -25,11 +25,11 @@ NetCaps::NetCaps() NetCaps::NetCaps(float pin_cap, float wire_cap, float fanout, - bool has_set_load) : + bool has_net_load) : pin_cap_(pin_cap), wire_cap_(wire_cap), fanout_(fanout), - has_set_load_(has_set_load) + has_net_load_(has_net_load) { } @@ -37,12 +37,12 @@ void NetCaps::init(float pin_cap, float wire_cap, float fanout, - bool has_set_load) + bool has_net_load) { pin_cap_ = pin_cap; wire_cap_ = wire_cap; fanout_ = fanout; - has_set_load_ = has_set_load; + has_net_load_ = has_net_load; } } // namespace diff --git a/dcalc/NetCaps.hh b/dcalc/NetCaps.hh index 76498492..ca1ad970 100644 --- a/dcalc/NetCaps.hh +++ b/dcalc/NetCaps.hh @@ -26,21 +26,21 @@ public: NetCaps(float pin_cap, float wire_cap, float fanout, - bool has_set_load); + bool has_net_load); void init(float pin_cap, float wire_cap, float fanout, - bool has_set_load); + bool has_net_load); float pinCap() const { return pin_cap_; } float wireCap() const{ return wire_cap_; } float fanout() const{ return fanout_; } - bool hasSetLoad() const { return has_set_load_; } + bool hasNetLoad() const { return has_net_load_; } private: float pin_cap_; float wire_cap_; float fanout_; - bool has_set_load_; + bool has_net_load_; }; } // namespace diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index c16d4519..62df813c 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -3050,9 +3050,11 @@ Sdc::drvrPinWireCap(const Pin *pin, { MinMaxFloatValues *values = drvr_pin_wire_cap_maps_[corner->index()].findKey(pin); if (values) - return values->value(min_max, cap, exists); - cap = 0.0; - exists = false; + values->value(min_max, cap, exists); + else { + cap = 0.0; + exists = false; + } } void From 118ab94f9a61f92f7af2f25d272ffc9bb24581af Mon Sep 17 00:00:00 2001 From: James Cherry Date: Wed, 11 Oct 2023 15:08:40 -0700 Subject: [PATCH 3/8] format Signed-off-by: James Cherry --- dcalc/GraphDelayCalc1.cc | 44 ++++++++++++++++++++-------------------- network/Network.cc | 2 +- sdc/Sdc.cc | 3 +-- 3 files changed, 24 insertions(+), 25 deletions(-) diff --git a/dcalc/GraphDelayCalc1.cc b/dcalc/GraphDelayCalc1.cc index a238242a..53566b45 100644 --- a/dcalc/GraphDelayCalc1.cc +++ b/dcalc/GraphDelayCalc1.cc @@ -577,27 +577,27 @@ GraphDelayCalc1::seedDrvrSlew(Vertex *drvr_vertex, Port *port = network_->port(drvr_pin); drive = sdc_->findInputDrive(port); } - for (auto tr : RiseFall::range()) { + for (auto rf : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { if (drive) { const MinMax *cnst_min_max = dcalc_ap->constraintMinMax(); const LibertyCell *drvr_cell; const LibertyPort *from_port, *to_port; float *from_slews; - drive->driveCell(tr, cnst_min_max, drvr_cell, from_port, + drive->driveCell(rf, cnst_min_max, drvr_cell, from_port, from_slews, to_port); if (drvr_cell) { if (from_port == nullptr) from_port = driveCellDefaultFromPort(drvr_cell, to_port); - findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, tr, + findInputDriverDelay(drvr_cell, drvr_pin, drvr_vertex, rf, from_port, from_slews, to_port, dcalc_ap); } else - seedNoDrvrCellSlew(drvr_vertex, drvr_pin, tr, drive, dcalc_ap, + seedNoDrvrCellSlew(drvr_vertex, drvr_pin, rf, drive, dcalc_ap, arc_delay_calc); } else - seedNoDrvrSlew(drvr_vertex, drvr_pin, tr, dcalc_ap, arc_delay_calc); + seedNoDrvrSlew(drvr_vertex, drvr_pin, rf, dcalc_ap, arc_delay_calc); } } } @@ -679,23 +679,23 @@ GraphDelayCalc1::seedLoadSlew(Vertex *vertex) vertex->name(sdc_network_)); ClockSet *clks = sdc_->findLeafPinClocks(pin); initSlew(vertex); - for (auto tr : RiseFall::range()) { + for (auto rf : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!vertex->slewAnnotated(tr, slew_min_max)) { + if (!vertex->slewAnnotated(rf, slew_min_max)) { float slew = 0.0; if (clks) { slew = slew_min_max->initValue(); ClockSet::Iterator clk_iter(clks); while (clk_iter.hasNext()) { Clock *clk = clk_iter.next(); - float clk_slew = clk->slew(tr, slew_min_max); + float clk_slew = clk->slew(rf, slew_min_max); if (slew_min_max->compare(clk_slew, slew)) slew = clk_slew; } } DcalcAPIndex ap_index = dcalc_ap->index(); - graph_->setSlew(vertex, tr, ap_index, slew); + graph_->setSlew(vertex, rf, ap_index, slew); } } } @@ -963,9 +963,9 @@ GraphDelayCalc1::initRootSlews(Vertex *vertex) for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); DcalcAPIndex ap_index = dcalc_ap->index(); - for (auto tr : RiseFall::range()) { - if (!vertex->slewAnnotated(tr, slew_min_max)) - graph_->setSlew(vertex, tr, ap_index, default_slew); + for (auto rf : RiseFall::range()) { + if (!vertex->slewAnnotated(rf, slew_min_max)) + graph_->setSlew(vertex, rf, ap_index, default_slew); } } } @@ -1161,12 +1161,12 @@ GraphDelayCalc1::netCaps(const Pin *drvr_pin, void GraphDelayCalc1::initSlew(Vertex *vertex) { - for (auto tr : RiseFall::range()) { + for (auto rf : RiseFall::range()) { for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - if (!vertex->slewAnnotated(tr, slew_min_max)) { + if (!vertex->slewAnnotated(rf, slew_min_max)) { DcalcAPIndex ap_index = dcalc_ap->index(); - graph_->setSlew(vertex, tr, ap_index, slew_min_max->initValue()); + graph_->setSlew(vertex, rf, ap_index, slew_min_max->initValue()); } } } @@ -1178,11 +1178,11 @@ GraphDelayCalc1::zeroSlewAndWireDelays(Vertex *drvr_vertex) for (auto dcalc_ap : corners_->dcalcAnalysisPts()) { DcalcAPIndex ap_index = dcalc_ap->index(); const MinMax *slew_min_max = dcalc_ap->slewMinMax(); - for (auto tr : RiseFall::range()) { + for (auto rf : RiseFall::range()) { // Init drvr slew. - if (!drvr_vertex->slewAnnotated(tr, slew_min_max)) { + if (!drvr_vertex->slewAnnotated(rf, slew_min_max)) { DcalcAPIndex ap_index = dcalc_ap->index(); - graph_->setSlew(drvr_vertex, tr, ap_index, slew_min_max->initValue()); + graph_->setSlew(drvr_vertex, rf, ap_index, slew_min_max->initValue()); } // Init wire delays and slews. @@ -1191,11 +1191,11 @@ GraphDelayCalc1::zeroSlewAndWireDelays(Vertex *drvr_vertex) Edge *wire_edge = edge_iter.next(); if (wire_edge->isWire()) { Vertex *load_vertex = wire_edge->to(graph_); - if (!graph_->wireDelayAnnotated(wire_edge, tr, ap_index)) - graph_->setWireArcDelay(wire_edge, tr, ap_index, 0.0); + if (!graph_->wireDelayAnnotated(wire_edge, rf, ap_index)) + graph_->setWireArcDelay(wire_edge, rf, ap_index, 0.0); // Init load vertex slew. - if (!load_vertex->slewAnnotated(tr, slew_min_max)) - graph_->setSlew(load_vertex, tr, ap_index, 0.0); + if (!load_vertex->slewAnnotated(rf, slew_min_max)) + graph_->setSlew(load_vertex, rf, ap_index, 0.0); } } } diff --git a/network/Network.cc b/network/Network.cc index b30cb24e..4180072d 100644 --- a/network/Network.cc +++ b/network/Network.cc @@ -1981,7 +1981,7 @@ CellIdLess::CellIdLess(const Network *network) : bool CellIdLess::operator()(const Cell *cell1, - const Cell *cell2) const + const Cell *cell2) const { return network_->id(cell1) < network_->id(cell2); } diff --git a/sdc/Sdc.cc b/sdc/Sdc.cc index 62df813c..51e2e20e 100644 --- a/sdc/Sdc.cc +++ b/sdc/Sdc.cc @@ -3121,9 +3121,8 @@ Sdc::connectedCap(const Pin *pin, pin_cap, wire_cap, fanout, has_net_load); float net_wire_cap; drvrPinWireCap(pin, corner, min_max, net_wire_cap, has_net_load); - if (has_net_load) { + if (has_net_load) wire_cap += net_wire_cap; - } } float From 9e75a7a9286ac2783560e6503e3e9d9c649f5e2f Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 16 Oct 2023 12:14:26 -0700 Subject: [PATCH 4/8] stringDelete rm debugging call Signed-off-by: James Cherry --- include/sta/StringUtil.hh | 1 - 1 file changed, 1 deletion(-) diff --git a/include/sta/StringUtil.hh b/include/sta/StringUtil.hh index c661d472..0b1e547d 100644 --- a/include/sta/StringUtil.hh +++ b/include/sta/StringUtil.hh @@ -148,7 +148,6 @@ stringDeleteCheck(const char *str); inline void stringDelete(const char *str) { - stringDeleteCheck(str); delete [] str; } From 29b94cc31d70f0ba375f08c14787616622e3dc47 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 16 Oct 2023 12:15:46 -0700 Subject: [PATCH 5/8] Corners::copy use copy constructor for parasitic_analysis_pts_ Signed-off-by: James Cherry --- search/Corner.cc | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/search/Corner.cc b/search/Corner.cc index e9abe7e0..072ec314 100644 --- a/search/Corner.cc +++ b/search/Corner.cc @@ -105,8 +105,7 @@ Corners::copy(Corners *corners) clear(); int index = 0; for (Corner *orig : corners->corners_) { - const char *name = orig->name(); - Corner *corner = new Corner(name, index); + Corner *corner = new Corner(orig->name(), index); corners_.push_back(corner); // Use the copied name in the map. corner_map_[corner->name()] = corner; @@ -120,17 +119,10 @@ Corners::copy(Corners *corners) parasitic_analysis_pts_.push_back(ap); } - int i = 0; - for (Corner *orig : corners->corners_) { + for (size_t i = 0; i < corners->corners_.size(); i++) { + Corner *orig = corners->corners_[i]; Corner *corner = corners_[i]; - auto &orig_aps = orig->parasitic_analysis_pts_; - auto &corner_aps = corner->parasitic_analysis_pts_; - corner_aps.resize(orig_aps.size()); - for (ParasiticAnalysisPt *orig_ap : orig_aps) { - int ap_index = orig_ap->index(); - corner_aps.push_back(parasitic_analysis_pts_[ap_index]); - } - i++; + corner->parasitic_analysis_pts_ = orig->parasitic_analysis_pts_; } } From b00ac00485bfb6a9b1f5641b9348ff3888593b2e Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 16 Oct 2023 18:46:08 -0700 Subject: [PATCH 6/8] report_power classify interface logic as macro Signed-off-by: James Cherry --- power/Power.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/power/Power.cc b/power/Power.cc index 1a313eac..92ea3ca6 100644 --- a/power/Power.cc +++ b/power/Power.cc @@ -219,7 +219,8 @@ Power::power(const Corner *corner, if (cell) { PowerResult inst_power = power(inst, cell, corner); if (cell->isMacro() - || cell->isMemory()) + || cell->isMemory() + || cell->interfaceTiming()) macro.incr(inst_power); else if (cell->isPad()) pad.incr(inst_power); From 8f5216dc13c1d6bd961b0ccce0acbd59d243096d Mon Sep 17 00:00:00 2001 From: James Cherry Date: Mon, 16 Oct 2023 20:44:39 -0700 Subject: [PATCH 7/8] read_power_activities escaped bus name issue Signed-off-by: James Cherry --- power/ReadVcdActivities.cc | 52 ++++++++++++++++++++------------------ power/VcdReader.cc | 8 ++++-- 2 files changed, 34 insertions(+), 26 deletions(-) diff --git a/power/ReadVcdActivities.cc b/power/ReadVcdActivities.cc index 8f53da0e..f151d75d 100644 --- a/power/ReadVcdActivities.cc +++ b/power/ReadVcdActivities.cc @@ -131,36 +131,42 @@ ReadVcdActivities::setVarActivity(VcdVar *var, string &var_name, const VcdValues &var_values) { - string sta_name = netVerilogToSta(var_name.c_str()); - if (var->width() == 1) + if (var->width() == 1) { + string sta_name = netVerilogToSta(var_name.c_str()); setVarActivity(sta_name.c_str(), var_values, 0); + } else { bool is_bus, is_range, subscript_wild; string bus_name; int from, to; - parseBusName(sta_name.c_str(), '[', ']', '\\', + parseBusName(var_name.c_str(), '[', ']', '\\', is_bus, is_range, bus_name, from, to, subscript_wild); - int value_bit = 0; - if (to < from) { - for (int bus_bit = to; bus_bit <= from; bus_bit++) { - string pin_name = bus_name; - pin_name += '['; - pin_name += to_string(bus_bit); - pin_name += ']'; - setVarActivity(pin_name.c_str(), var_values, value_bit); - value_bit++; - } - } - else { - for (int bus_bit = to; bus_bit >= from; bus_bit--) { - string pin_name = bus_name; - pin_name += '['; - pin_name += to_string(bus_bit); - pin_name += ']'; - setVarActivity(pin_name.c_str(), var_values, value_bit); - value_bit++; + if (is_bus) { + string sta_bus_name = netVerilogToSta(bus_name.c_str()); + int value_bit = 0; + if (to < from) { + for (int bus_bit = to; bus_bit <= from; bus_bit++) { + string pin_name = sta_bus_name; + pin_name += '['; + pin_name += to_string(bus_bit); + pin_name += ']'; + setVarActivity(pin_name.c_str(), var_values, value_bit); + value_bit++; + } + } + else { + for (int bus_bit = to; bus_bit >= from; bus_bit--) { + string pin_name = sta_bus_name; + pin_name += '['; + pin_name += to_string(bus_bit); + pin_name += ']'; + setVarActivity(pin_name.c_str(), var_values, value_bit); + value_bit++; + } } } + else + report_->warn(807, "problem parsing bus %s.", var_name.c_str()); } } @@ -185,8 +191,6 @@ ReadVcdActivities::setVarActivity(const char *pin_name, else { power_->setUserActivity(pin, activity, duty, PwrActivityOrigin::user); - if (annotated_pins_.hasKey(pin)) - printf("luse\n"); annotated_pins_.insert(pin); } } diff --git a/power/VcdReader.cc b/power/VcdReader.cc index 8c6ff5c8..7d990dee 100644 --- a/power/VcdReader.cc +++ b/power/VcdReader.cc @@ -194,7 +194,7 @@ VcdReader::parseVar() type_name.c_str()); else { int width = stoi(tokens[1]); - string id = tokens[2]; + string &id = tokens[2]; string name; for (string &context : scope_) { @@ -203,8 +203,12 @@ VcdReader::parseVar() } name += tokens[3]; // iverilog separates bus base name from bit range. - if (tokens.size() == 5) + if (tokens.size() == 5) { + // Preserve space after esacaped name. + if (name[0] == '\\') + name += ' '; name += tokens[4]; + } vcd_->makeVar(name, type, width, id); } From fa650706827c4d42bef19ac0becb7dbe92bd98d2 Mon Sep 17 00:00:00 2001 From: James Cherry Date: Tue, 17 Oct 2023 14:29:38 -0700 Subject: [PATCH 8/8] write_timing_model unclocked register seg fault Signed-off-by: James Cherry --- search/ClkSkew.cc | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/search/ClkSkew.cc b/search/ClkSkew.cc index 03c1019f..217b536c 100644 --- a/search/ClkSkew.cc +++ b/search/ClkSkew.cc @@ -370,14 +370,16 @@ ClkSkews::findClkDelays(const Clock *clk, while (path_iter.hasNext()) { PathVertex *path = path_iter.next(); const ClockEdge *path_clk_edge = path->clkEdge(this); - const RiseFall *clk_rf = path_clk_edge->transition(); - const Clock *path_clk = path_clk_edge->clock(); - if (path_clk == clk) { - Arrival arrival = path->arrival(this); - Delay clk_delay = delayAsFloat(arrival) - path_clk_edge->time(); - const MinMax *min_max = path->minMax(this); - const RiseFall *rf = path->transition(this); - delays[clk_rf->index()][rf->index()].setValue(min_max, clk_delay); + if (path_clk_edge) { + const RiseFall *clk_rf = path_clk_edge->transition(); + const Clock *path_clk = path_clk_edge->clock(); + if (path_clk == clk) { + Arrival arrival = path->arrival(this); + Delay clk_delay = delayAsFloat(arrival) - path_clk_edge->time(); + const MinMax *min_max = path->minMax(this); + const RiseFall *rf = path->transition(this); + delays[clk_rf->index()][rf->index()].setValue(min_max, clk_delay); + } } } }