238 lines
7.8 KiB
Plaintext
238 lines
7.8 KiB
Plaintext
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PASS: basic setup
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PASS: global timing derate
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PASS: rise/fall timing derate
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PASS: data path derate
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PASS: clock path derate
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PASS: cell_delay derate
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PASS: net_delay derate
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PASS: cell-specific derate
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PASS: instance-specific derate
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.09 0.09 ^ reg2/Q (DFF_X1)
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0.00 0.09 ^ out1 (out)
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0.09 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.09 data arrival time
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---------------------------------------------------------
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6.91 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report_checks after derate
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PASS: unset_timing_derate
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PASS: disable timing instance buf1
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: out1 (output port clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 ^ reg1/CK (DFF_X1)
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0.08 10.08 v reg1/Q (DFF_X1)
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0.00 10.08 v reg3/D (DFF_X1)
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10.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg3/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-10.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: report after disable buf1
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PASS: unset_disable_timing buf1
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PASS: disable timing pin buf1/A
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PASS: unset disable pin buf1/A
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PASS: disable lib cell from/to
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PASS: unset disable lib cell from/to
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PASS: disable lib cell all arcs
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PASS: unset disable lib cell all arcs
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PASS: set_driving_cell BUF_X1
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PASS: set_driving_cell INV_X1 -pin ZN
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PASS: set_driving_cell -rise
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PASS: set_driving_cell -fall
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PASS: set_drive 100
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PASS: set_drive -rise 80
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PASS: set_drive -fall 120
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PASS: set_drive 0 (ideal)
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PASS: input transitions
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PASS: clock insertion (source latency)
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PASS: clock insertion -rise -max
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PASS: clock insertion -fall -min
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PASS: clock insertion -rise -min
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PASS: clock insertion -fall -max
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PASS: clock insertion -early
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PASS: clock insertion -late
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PASS: source latency with all corners
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PASS: network latency with all corners
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PASS: set_load various options
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PASS: set_resistance
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PASS: clock gating check on clock
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Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found.
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Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found.
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PASS: clock gating check on design
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PASS: set_max_time_borrow clock
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PASS: set_max_time_borrow pin
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PASS: set_data_check -setup
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PASS: set_data_check -hold
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PASS: set_ideal_network
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PASS: set_ideal_transition
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PASS: set_wire_load_mode top
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PASS: set_wire_load_mode enclosed
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PASS: set_wire_load_mode segmented
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PASS: set_wire_load_model 1K
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PASS: set_wire_load_model 5K
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PASS: set_min_pulse_width clock
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PASS: set_min_pulse_width -high
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PASS: set_min_pulse_width -low
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Startpoint: in1 (input port clocked by clk1)
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Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1)
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Path Group: clk1
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk1 (rise edge)
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1.00 1.00 clock network delay (ideal)
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2.00 3.00 v input external delay
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0.00 3.00 v in1 (in)
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0.03 3.03 v buf1/Z (BUF_X1)
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0.05 3.08 v or1/ZN (OR2_X1)
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0.03 3.10 ^ nor1/ZN (NOR2_X1)
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0.00 3.10 ^ reg2/D (DFF_X1)
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3.10 data arrival time
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0.00 0.00 clock clk1 (rise edge)
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0.20 0.20 clock network delay (propagated)
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0.00 0.20 clock reconvergence pessimism
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0.20 ^ reg1/CK (DFF_X1)
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0.28 0.48 v reg1/Q (DFF_X1)
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-0.50 -0.02 data check setup time
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-0.02 data required time
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---------------------------------------------------------
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-0.02 data required time
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-3.10 data arrival time
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---------------------------------------------------------
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-3.13 slack (VIOLATED)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
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Path Group: clk2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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10.00 10.00 clock clk1 (rise edge)
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1.00 11.00 clock network delay (ideal)
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0.00 11.00 ^ reg1/CK (DFF_X1)
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0.08 11.08 v reg1/Q (DFF_X1)
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0.00 11.08 v reg3/D (DFF_X1)
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11.08 data arrival time
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20.00 20.00 clock clk2 (rise edge)
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0.30 20.30 clock network delay (ideal)
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0.00 20.30 clock reconvergence pessimism
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20.30 ^ reg3/CK (DFF_X1)
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-0.04 20.26 library setup time
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20.26 data required time
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---------------------------------------------------------
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20.26 data required time
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-11.08 data arrival time
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---------------------------------------------------------
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9.18 slack (MET)
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PASS: final report_checks
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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nor1/ZN 0.20 0.01 0.18 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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nor1/ZN 26.70 1.45 25.25 (MET)
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PASS: report_check_types
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ALL PASSED
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