PASS: basic setup PASS: global timing derate PASS: rise/fall timing derate PASS: data path derate PASS: clock path derate PASS: cell_delay derate PASS: net_delay derate PASS: cell-specific derate PASS: instance-specific derate Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.09 0.09 ^ reg2/Q (DFF_X1) 0.00 0.09 ^ out1 (out) 0.09 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.09 data arrival time --------------------------------------------------------- 6.91 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: report_checks after derate PASS: unset_timing_derate PASS: disable timing instance buf1 Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: report after disable buf1 PASS: unset_disable_timing buf1 PASS: disable timing pin buf1/A PASS: unset disable pin buf1/A PASS: disable lib cell from/to PASS: unset disable lib cell from/to PASS: disable lib cell all arcs PASS: unset disable lib cell all arcs PASS: set_driving_cell BUF_X1 PASS: set_driving_cell INV_X1 -pin ZN PASS: set_driving_cell -rise PASS: set_driving_cell -fall PASS: set_drive 100 PASS: set_drive -rise 80 PASS: set_drive -fall 120 PASS: set_drive 0 (ideal) PASS: input transitions PASS: clock insertion (source latency) PASS: clock insertion -rise -max PASS: clock insertion -fall -min PASS: clock insertion -rise -min PASS: clock insertion -fall -max PASS: clock insertion -early PASS: clock insertion -late PASS: source latency with all corners PASS: network latency with all corners PASS: set_load various options PASS: set_resistance PASS: clock gating check on clock Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found. Warning: sdc_advanced.tcl line 1, object 'sdc_test2' not found. PASS: clock gating check on design PASS: set_max_time_borrow clock PASS: set_max_time_borrow pin PASS: set_data_check -setup PASS: set_data_check -hold PASS: set_ideal_network PASS: set_ideal_transition PASS: set_wire_load_mode top PASS: set_wire_load_mode enclosed PASS: set_wire_load_mode segmented PASS: set_wire_load_model 1K PASS: set_wire_load_model 5K PASS: set_min_pulse_width clock PASS: set_min_pulse_width -high PASS: set_min_pulse_width -low Startpoint: in1 (input port clocked by clk1) Endpoint: reg2 (falling edge-triggered data to data check clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 1.00 1.00 clock network delay (ideal) 2.00 3.00 v input external delay 0.00 3.00 v in1 (in) 0.03 3.03 v buf1/Z (BUF_X1) 0.05 3.08 v or1/ZN (OR2_X1) 0.03 3.10 ^ nor1/ZN (NOR2_X1) 0.00 3.10 ^ reg2/D (DFF_X1) 3.10 data arrival time 0.00 0.00 clock clk1 (rise edge) 0.20 0.20 clock network delay (propagated) 0.00 0.20 clock reconvergence pessimism 0.20 ^ reg1/CK (DFF_X1) 0.28 0.48 v reg1/Q (DFF_X1) -0.50 -0.02 data check setup time -0.02 data required time --------------------------------------------------------- -0.02 data required time -3.10 data arrival time --------------------------------------------------------- -3.13 slack (VIOLATED) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 1.00 11.00 clock network delay (ideal) 0.00 11.00 ^ reg1/CK (DFF_X1) 0.08 11.08 v reg1/Q (DFF_X1) 0.00 11.08 v reg3/D (DFF_X1) 11.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.30 20.30 clock network delay (ideal) 0.00 20.30 clock reconvergence pessimism 20.30 ^ reg3/CK (DFF_X1) -0.04 20.26 library setup time 20.26 data required time --------------------------------------------------------- 20.26 data required time -11.08 data arrival time --------------------------------------------------------- 9.18 slack (MET) PASS: final report_checks max slew Pin Limit Slew Slack ------------------------------------------------------------ nor1/ZN 0.20 0.01 0.18 (MET) max capacitance Pin Limit Cap Slack ------------------------------------------------------------ nor1/ZN 26.70 1.45 25.25 (MET) PASS: report_check_types ALL PASSED