2018-09-28 17:54:21 +02:00
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// OpenSTA, Static Timing Analyzer
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2020-03-07 03:50:37 +01:00
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// Copyright (c) 2020, Parallax Software, Inc.
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2018-09-28 17:54:21 +02:00
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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2020-04-05 20:35:51 +02:00
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#include "sdc/PortDelay.hh"
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#include "sdc/Sdc.hh"
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#include "network/Network.hh"
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2018-09-28 17:54:21 +02:00
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namespace sta {
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PortDelay::PortDelay(Pin *pin,
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ClockEdge *clk_edge,
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Pin *ref_pin) :
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pin_(pin),
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clk_edge_(clk_edge),
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source_latency_included_(false),
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network_latency_included_(false),
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ref_pin_(ref_pin),
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delays_()
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{
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}
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Clock *
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PortDelay::clock() const
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{
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if (clk_edge_)
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return clk_edge_->clock();
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else
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2019-03-13 01:25:53 +01:00
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return nullptr;
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2018-09-28 17:54:21 +02:00
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}
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bool
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PortDelay::sourceLatencyIncluded() const
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{
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return source_latency_included_;
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}
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void
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PortDelay::setSourceLatencyIncluded(bool included)
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{
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source_latency_included_ = included;
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}
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bool
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PortDelay::networkLatencyIncluded() const
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{
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return network_latency_included_;
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}
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void
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PortDelay::setNetworkLatencyIncluded(bool included)
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{
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network_latency_included_ = included;
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}
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2019-11-11 23:30:19 +01:00
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RiseFall *
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2018-09-28 17:54:21 +02:00
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PortDelay::refTransition() const
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{
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// Reference pin transition is the clock transition.
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if (clk_edge_)
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return clk_edge_->transition();
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else
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2019-11-11 23:30:19 +01:00
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return RiseFall::rise();
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2018-09-28 17:54:21 +02:00
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}
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InputDelay::InputDelay(Pin *pin,
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ClockEdge *clk_edge,
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Pin *ref_pin,
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int index,
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Network *network) :
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PortDelay(pin, clk_edge, ref_pin),
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index_(index)
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{
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2019-10-25 17:51:59 +02:00
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findLeafLoadPins(pin, network, &leaf_pins_);
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2018-09-28 17:54:21 +02:00
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}
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OutputDelay::OutputDelay(Pin *pin,
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ClockEdge *clk_edge,
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Pin *ref_pin,
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Network *network) :
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2019-11-11 01:10:26 +01:00
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PortDelay(pin, clk_edge, ref_pin)
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2018-09-28 17:54:21 +02:00
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{
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if (network)
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2019-10-25 17:51:59 +02:00
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findLeafDriverPins(pin, network, &leaf_pins_);
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2018-09-28 17:54:21 +02:00
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}
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////////////////////////////////////////////////////////////////
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PortDelayLess::PortDelayLess(const Network *network) :
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network_(network)
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{
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}
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bool
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PortDelayLess::operator() (const PortDelay *delay1,
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const PortDelay *delay2) const
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{
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Pin *pin1 = delay1->pin();
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Pin *pin2 = delay2->pin();
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int pin_cmp = network_->pathNameCmp(pin1, pin2);
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if (pin_cmp < 0)
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return true;
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else if (pin_cmp > 0)
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return false;
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else
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return clkEdgeLess(delay1->clkEdge(), delay2->clkEdge());
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}
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} // namespace
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