2018-10-24 01:24:22 +02:00
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Release 2.0 Patches
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2018/10/23 spash msg embedded quotes seg fault
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2018/10/23 read_verilog mod inst with no ports seg fault
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2018-11-09 19:04:16 +01:00
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2018/11/08 corners > 2 causes internal error
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2018/11/09 Verilog ignore attributes (* blah *)
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2018-12-26 20:03:31 +01:00
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2018/12/24 all_fanout from input port
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2019-01-04 01:14:15 +01:00
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2018/12/25 liberty pg_types
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2019/01/03 liberty 2D bus names
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2019-01-08 07:15:17 +01:00
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2019/01/07 WritePathSpice don't barf on spice subckts missing liberty cells
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2019-02-19 07:32:59 +01:00
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2019/01/15 generated clk -divide_by 16384 cycle accting
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2019/01/18 write_path_spice ground coupling caps
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2019/01/18 write_path_spice do not write zero caps
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2019/01/19 write_path_spice tie-offs for demorgan'd nand/nor functs
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2019/01/29 write_sdc set_driving_cell omit -library if missing from sdc
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2019/01/31 generated clk -divide_by 16384 cycle accting fallout
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2019/02/17 report_power internal power accuracy
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2019/02/18 write_path_spice first line is comment
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